L6228Q ,PowerSPIN: DMOS driver for bipolar stepper motorFeatures■ Operating supply voltage from 8 to 52 V■ 2.8 A output peak current (1.4 A )r.m.s.■ R 0.73 ..
L6229N ,DMOS DRIVER FOR THREE-PHASE BRUSHLESS DC MOTORFEATURES■ OPERATING SUPPLY VOLTAGE FROM 8 TO 52V■ 2.8A OUTPUT PEAK CURRENT (1.4A DC)■ R 0.73Ω TYP. ..
L6229PD ,DMOS DRIVER FOR THREE-PHASE BRUSHLESS DC MOTORAbsolute Maximum RatingsSymbol Parameter Test conditions Value UnitV Supply Voltage V = V = V 60 VS ..
L6229Q ,PowerSPIN: DMOS driver for three-phase brushless DC motorElectrical characteristics . . . . . 85 Circuit description . . 115.1 Power stages and ch ..
L6229QTR ,PowerSPIN: DMOS driver for three-phase brushless DC motorFeatures■ Operating supply voltage from 8 to 52 V■ 2.8 A output peak current (1.4 A RMS)■ R 0.73 Ω ..
L6230 ,PowerSPIN: DMOS driver for three-phase brushless DC motorFeatures■ Operating supply voltage from 8 to 52 V■ 2.8 A output peak current (1.4 A RMS)■ R 0.73 Ω ..
LC321664BT-70 ,1 MEG (65536 words X 16 bits) DRAM Fast Page Mode, Byte WriteOrdering number : EN5082AOve rviewThe LC321664BJ, BM, BT is a CMOS dynamic RAMoperating on a single ..
LC322260J-70 ,2 MEG (131072 words x 16 bits) DRAM fast page mode, byte reed/writePin assignment conforms to the JEDEC standards for4M DRAM (262144 words x 16 bits, 2C-AsnCrgtype). ..
LC322260J-80 ,2 MEG (131072 words x 16 bits) DRAM fast page mode, byte reed/writeAbsolute Maximum RatingsParameter Symbol Ratings Unit NoteMaximum supply voltage Vcc max -IOto +7.0 ..
LC322271M-80 ,2MEG (131072words x 16bit) DRAM fast page mode, byte writeElectrical Characteristics at Ta = 0 to +70°C, V = 5 V ± 10%CCLC322271J, M, TParameter Symbol Condi ..
LC32464M-80 ,256K (65536 words X 4 bits) DRAM Fast Page ModeFeatures. 65536 words K 4 bits configuration.. RAS access time/cycle time/power dissipation256 K (6 ..
LC32464P-80 ,256K (65536 words x 4 bit) DRAM fast page modeBlock DiagramR A S o---- Clock generator No,1 ___-__- (w --C) v C CCAS Cy- 9., Clock generalorNo. 2 ..
L6228Q
PowerSPIN: DMOS driver for bipolar stepper motor
Doc ID 14321 Rev 5 1/32
L6228QDMOS driver for bipolar stepper motor
Datasheet − production data
Features Operating supply voltage from 8 to 52 V 2.8 A output peak current (1.4 Ar.m.s.) RDS(on) 0.73 Ω typ. value @ TJ = 25 °C Operating frequency up to 100 kHz Non dissipative overcurrent protection Dual independent constant tOFF PWM current
controllers Fast/slow decay mode selection Fast decay quasi-synchronous rectification Decoding logic for stepper motor full and half-
step drive Cross conduction protection Thermal shutdown Undervoltage lockout Integrated fast free wheeling diodes
Applications Bipolar stepper motor
DescriptionThe L6228Q is a DMOS fully integrated stepper
motor driver with non-dissipative overcurrent
protection, realized in BCD multipower
technology, which combines isolated DMOS
power transistors with CMOS and bipolar circuits
on the same chip. The device includes all the
circuitry needed to drive a two-phase bipolar
stepper motor including: a dual DMOS full-bridge,
the constant off-time PWM current controller that
performs the chopping regulation and the phase
sequence generator, that generates the stepping
sequence. Available in VFQFPN32 5 mm x 5 mm
package, the L6228Q features a non-dissipative
overcurrent protection on the high-side power
MOSFETs and thermal shutdown.
Figure 1. Block diagram
Contents L6228Q2/32 Doc ID 14321 Rev 5
Contents Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114.1 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.3 PWM current control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
4.4 Decay modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
4.5 Stepping sequence generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.6 Half-step mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
4.7 Normal drive mode (full-step two-phase-on) . . . . . . . . . . . . . . . . . . . . . . 18
4.8 Wave drive mode (full-step one-phase-on) . . . . . . . . . . . . . . . . . . . . . . . 18
4.9 Non-dissipative overcurrent protection . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
4.10 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Output current capability and IC power dissipation . . . . . . . . . . . . . . 25 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
L6228Q Electrical data
Doc ID 14321 Rev 5 3/32
1 Electrical data
1.1 Absolute maximum ratings
1.2 Recommended operating conditions
Table 1. Absolute maximum ratings
Table 2. Recommended operating conditions
Electrical data L6228Q
4/32 Doc ID 14321 Rev 5
1.3 Thermal data
Table 3. Thermal data Mounted on a double-layer FR4 PCB with a dissipating copper surface of 0.5 cm2 on the top side plus 6 2 ground layer connected through 18 via holes (9 below the IC).
L6228Q Pin connection
Doc ID 14321 Rev 5 5/32
2 Pin connection
Figure 2. Pin connection (top view)
Note: 1 The pins from 2 to 8 are connected to die PAD. The die PAD must be connected to GND pin.
Pin connection L6228Q
6/32 Doc ID 14321 Rev 5
Table 4. Pin description Also connected to the output drain of the overcurrent and thermal protection MOSFET. Therefore, it has to be driven putting
in series a resistor with a value in the range from 2.2 kΩ to180 kΩ, recommended 100 kΩ.
L6228Q Electrical characteristics
Doc ID 14321 Rev 5 7/32
3 Electrical characteristics
Table 5. Electrical characteristics (TA = 25 °C, Vs = 48 V , unless otherwise specified)
Electrical characteristics L6228Q
8/32 Doc ID 14321 Rev 5 Tested at 25 °C in a restricted range and guaranteed by characterization. See Figure3. See Figure4. See Figure5. See Figure6. Applying a voltage of 1 V to pin SENSE and a voltage drop from 2 V to 0 V to pin VREF. See Figure7.
Table 5. Electrical characteristics (continued) (TA = 25 °C, Vs = 48 V, unless otherwise specified)
L6228Q Electrical characteristics
Doc ID 14321 Rev 5 9/32
Figure 3. Switching characteristic definition
Figure 4. Clock to output delay time
Figure 5. Minimum timing definition - clock input
Electrical characteristics L6228Q
10/32 Doc ID 14321 Rev 5
Figure 6. Minimum timing definition - logic inputs
Figure 7. Overcurrent detection timing definition
L6228Q Circuit description
Doc ID 14321 Rev 5 11/32
4 Circuit description
4.1 Power stages and charge pump
The L6228Q integrates two independent power MOSFET full-bridges. Each power MOSFET
has an RDS(on) = 0.73 Ω (typical value @ 25 °C), with intrinsic fast freewheeling diode.
Switching patterns are generated by the PWM current controller and the phase sequence
generator (see below). Cross conduction protection is achieved using a dead time (tDT = 1 μs
typical value) between the switch off and switch on of two power MOSFETs in one leg of a
bridge.
VSA and VSB pins must be connected together to the supply voltage VS. The device
operates with a supply voltage in the range from 8 V to 52 V. It has to be noticed that the
RDS(on) increases of some percents when the supply voltage is in the range from 8 V to 12
Using N-channel power MOSFETs for the upper transistors in the bridge requires a gate
drive voltage above the power supply voltage. The bootstrapped supply voltage VBOOT is
obtained through an internal oscillator and few external components to realize a charge
pump circuit as shown in Figure 8. The oscillator output (VCP) is a square wave at 600 kHz
(typical) with 10 V amplitude. Recommended values/part numbers for the charge pump
circuit are shown in Table6.
Figure 8. Charge pump circuit
Table 6. Charge pump external component values
Circuit description L6228Q
12/32 Doc ID 14321 Rev 5
4.2 Logic inputs
Pins CONTROL, HALF/FULL, CLOCK, RESET and CW/CCW are TTL/CMOS and
microcontroller compatible logic inputs. The internal structure is shown in Figure 9. Turn-on
and turn-off threshold typical values are respectively Vth(ON)= 1.8 V and Vth(OFF)= 1.3 V.
Pin EN (Enable) has identical input structure with the exception that the drain of the
overcurrent and thermal protection MOSFET is also connected to this pin. Due to this
connection, this pin has to be driven carefully. The EN input may be driven in one of two
configurations as shown in Figure 10 or Figure 11. If driven by an open drain (collector)
structure, a pull-up resistor REN and a capacitor CEN are connected as shown in Figure 10.
If the driver is a standard Push-Pull structure the resistor REN and the capacitor CEN are
connected as shown in Figure 11. The resistor REN should be chosen in the range from 2.2
kΩ to 180 kΩ . REN and CEN recommended values are respectively 100 kΩ and 5.6 nF.
Figure 9. Logic input internal structure
Figure 10. EN pin open collector driving
Figure 11. EN pin push-pull driving
L6228Q Circuit description
4.3 PWM current control
The L6228Q includes a constant off-time PWM current controller for each of the two
bridges. The current control circuit senses the bridge current, by monitoring the voltage drop
across an external sense resistor connected between the source of the two lower power
MOSFET transistors and ground, as shown in Figure 12. As the current in the motor builds
up the voltage across the sense resistor increases proportionally. When the voltage drop
across, the sense resistor becomes greater than the voltage at the reference input (VREFA
or VREFB) the sense comparator triggers the monostable switching the bridge off. The
power MOSFETs remain off for the time set by the monostable and the motor current
recirculates as defined by the selected decay mode, described in the next section. When the
monostable times out, the bridge turns on again. Since the internal dead time, used to
prevent cross conduction in the bridge, delays the turn-on of the power MOSFET, the
effective off-time is the sum of the monostable time plus the dead time.
Figure 12. PWM current controller simplified schematic
Figure 13 shows the typical operating waveforms of the output current, the voltage drop
across the sensing resistor, the RC pin voltage and the status of the bridge. More details
regarding the synchronous rectification and the output stage configuration are included in
the next section.
Immediately after the power MOSFET turns on, a high peak current flows through the
sensing resistor due to the reverse recovery of the freewheeling diodes. The L6228Q
provides a 1 μs blanking time tBLANK that inhibits the comparator output so that this current
spike cannot prematurely re-trigger the monostable.
Circuit description L6228Q
Figure 13. Output current regulation waveforms
Figure 14 shows the magnitude of the off-time tOFF versus COFF and ROFF values. It can be
approximately calculated from the equations:
tRCFALL = 0.6 · ROFF · COFF
tOFF = tRCFALL + tDT = 0.6 · ROFF · COFF + tDT
where ROFF and COFF are the external component values and tDT is the internally generated
Dead Time with:
20 kΩ ≤ ROFF ≤ 100 kΩ
0.47 nF ≤ COFF ≤ 100 nF
tDT = 1 µs (typical value)
Therefore:
L6228Q Circuit description
Doc ID 14321 Rev 5 15/32
Circuit description L6228Q
16/32 Doc ID 14321 Rev 5
Figure 15. Area where tON can vary maintaining the PWM regulation
4.4 Decay modes
The CONTROL input is used to select the behavior of the bridge during the off-time. When
the CONTROL pin is low, the fast decay mode is selected and both transistors in the bridge
are switched off during the off-time. When the CONTROL pin is high, the slow decay mode
is selected and only the low-side transistor of the bridge is switched off during the off-time.
Figure 16 shows the operation of the bridge in the fast decay mode. At the start of the off-
time, both of the power MOSFETs are switched off and the current recirculates through the
two opposite free wheeling diodes. The current decays with a high dI/dt since the voltage
across the coil is essentially the power supply voltage. After the dead time, the lower power
MOSFET, in parallel with the conducting diode, is turned on in synchronous rectification
mode. In applications where the motor current is low, it is possible for the current to decay
completely to zero during the off-time. At this point, if both of the power MOSFETs were
operating in the synchronous rectification mode it would be possible for the current to build
in the opposite direction. T o prevent this, the lower power MOSFET is operated in
synchronous rectification mode only. This operation is called quasi-synchronous rectification
mode. When the monostable times out, the power MOSFETs are turned on again after
some delay set by the dead time to prevent cross conduction.
Figure 17 shows the operation of the bridge in the slow decay mode. At the start of the off-
time, the lower power MOSFET is switched off and the current recirculates around the upper
half of the bridge. Since the voltage across the coil is low, the current decays slowly. After
the dead time, the upper power MOSFET is operated in the synchronous rectification mode.
When the monostable times out, the lower power MOSFET is turned on again after some
delay set by the dead time to prevent cross conduction.
