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L6226Q-L6226QTR
PowerSPIN: DMOS dual full bridge driver
August 2010 Doc ID 14335 Rev 5 1/29
L6226QDMOS dual full bridge driver
Features Operating supply voltage from 8 to 52 V 2.8 A output peak current (1.4 A DC) RDS(on) 0.73 Ω typ. value @ TJ = 25 °C Operating frequency up to 100 kHz Programmable high side overcurrent detection
and protection Diagnostic output Paralleled operation Cross conduction protection Thermal shutdown Under voltage lockout Integrated fast free wheeling diodes
Applications Bipolar stepper motor Dual or quad DC motor
DescriptionThe L6226Q is a DMOS dual full bridge designed
for motor control applications, realized in
BCDmultipower technology, which combines
isolated DMOS power transistors with CMOS and
bipolar circuits on the same chip. Available in
QFN32 5x5 package, the L6226Q features
thermal shutdown and a non-dissipative
overcurrent detection on the high side power
MOSFETs plus a diagnostic output that can be
easily used to implement the overcurrent
protection.
Figure 1. Block diagram
Contents L6226Q2/29 Doc ID 14335 Rev 5
Contents Electrical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31.1 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.2 Recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
1.3 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Circuit description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104.1 Power stages and charge pump . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
4.2 Logic inputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
4.3 T ruth table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
4.4 Non-dissipative overcurrent detection and protection . . . . . . . . . . . . . . . 12
4.5 Thermal protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Paralleled operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Output current capability and IC power dissipation . . . . . . . . . . . . . . 23 Thermal management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
L6226Q Electrical data
Doc ID 14335 Rev 5 3/29
1 Electrical data
1.1 Absolute maximum ratings
1.2 Recommended operating conditions
Table 1. Absolute maximum ratings
Table 2. Recommended operating conditions
Electrical data L6226Q
4/29 Doc ID 14335 Rev 5
1.3 Thermal data
Table 3. Thermal data Mounted on a double-layer FR4 PCB with a dissipating copper surface of 0.5 cm2 on the top side plus 6 2 ground layer connected through 18 via holes (9 below the IC).
L6226Q Pin connection
Doc ID 14335 Rev 5 5/29
2 Pin connection
Figure 2. Pin connection (top view)
Note: 1 The pins 2 to 8 are connected to die PAD. The die PAD must be connected to GND pin.
Pin connection L6226Q
6/29 Doc ID 14335 Rev 5
Table 4. Pin description
L6226Q Electrical characteristics
Doc ID 14335 Rev 5 7/29
3 Electrical characteristics
TA = 25 °C, Vs = 48 V, unless otherwise specified
Table 5. Electrical characteristics
Electrical characteristics L6226Q
8/29 Doc ID 14335 Rev 5
Figure 3. Switching characteristic definition Tested at 25 °C in a restricted range and guaranteed by characterization. See Figure3 See Figure4
Table 5. Electrical characteristics (continued)
L6226Q Electrical characteristics
Doc ID 14335 Rev 5 9/29
Figure 4. Overcurrent detection timing definition
Circuit description L6226Q
10/29 Doc ID 14335 Rev 5
4 Circuit description
4.1 Power stages and charge pump
The L6226Q integrates two independent power MOS full bridges. Each power MOS has an
RDS(on) = 0.73 Ω (typical value @ 25 °C), with intrinsic fast freewheeling diode. Cross
conduction protection is achieved using a dead time (td = 1 μs typical) between the switch
off and switch on of two power MOS in one leg of a bridge.
Using N-channel power MOS for the upper transistors in the bridge requires a gate drive
voltage above the power supply voltage. The bootstrapped (VBOOT) supply is obtained
through an internal oscillator and few external components to realize a charge pump circuit
as shown in Figure 5. The oscillator output (VCP) is a square wave at 600 kHz (typical) with
10 V amplitude. Recommended values/part numbers for the charge pump circuit are shown
in Table6.
Figure 5. Charge pump circuit
Table 6. Charge pump external components values
L6226Q Circuit description
Doc ID 14335 Rev 5 11/29
4.2 Logic inputs
Pins IN1A, IN2A, IN1B, IN2B, ENA and ENB are TTL/CMOS and microcontroller compatible
logic inputs. The internal structure is shown in Figure 6. Typical value for turn-on and turn-off
thresholds are respectively Vthon = 1.8 V and Vthoff = 1.3 V.
Pins ENA and ENB are commonly used to implement overcurrent and thermal protection by
connecting them respectively to the outputs OCDA and OCDB, which are open-drain
outputs. If that type of connection is chosen, some care needs to be taken in driving these
pins. Two configurations are shown in Figure 7 and Figure 8. If driven by an open drain
(collector) structure, a pull-up resistor REN and a capacitor CEN are connected as shown in
Figure 7. If the driver is a standard push-pull structure the resistor REN and the capacitor
CEN are connected as shown in Figure 8. The resistor REN should be chosen in the range
from 2.2 kΩ to 180 kΩ. Recommended values for REN and CEN are respectively 100 kΩ and
5.6 nF . More information on selecting the values is found in the overcurrent protection
section.
Figure 6. Logic inputs internal structure
Figure 7. ENA and ENB pins open collector driving
Figure 8. ENA and ENB pins push-pull driving
Circuit description L6226Q
12/29 Doc ID 14335 Rev 5
4.3 Truth table
4.4 Non-dissipative overcurrent detection and protection
An overcurrent detection circuit (OCD) is integrated. This circuit can be used to provides
protection against a short circuit to ground or between two phases of the bridge as well as a
roughly regulation of the load current. With this internal over current detection, the external
current sense resistor normally used and its associated power dissipation are eliminated.
Figure 9 shows a simplified schematic of the overcurrent detection circuit for the bridge A.
bridge B is provided of an analogous circuit. o implement the over current detection, a sensing element that delivers a small but precise
fraction of the output current is implemented with each high side power MOS. Since this
current is a small fraction of the output current there is very little additional power
dissipation. This current is compared with an internal reference current IREF . When the
output current reaches the detection threshold Isover the OCD comparator signals a fault
condition. When a fault condition is detected, an internal open drain MOS with a pull down
capability of 4 mA connected to OCD pin is turned on. Figure 10 shows the OCD operation.
This signal can be used to regulate the output current simply by connecting the OCD pin to
EN pin and adding an external R-C as shown in Figure 9. The off time before recovering
normal operation can be easily programmed by means of the accurate thresholds of the
logic inputs.
IREF and, therefore, the output current detection threshold are selectable by RCL value,
following the equations: Isover = 2.8 A ± 30 % at -25 °C < TJ < 125 °C if RCL = 0 Ω
(PROGCL connected to GND) Isover = ±10 % at -25 °C < TJ < 125 °C if 5 kΩ < RCL < 40 kΩ
Figure 11 shows the output current protection threshold versus RCL value in the range 5 kΩ
to 40 kΩ.
The disable time tDISABLE before recovering normal operation can be easily programmed by
means of the accurate thresholds of the logic inputs. It is affected whether by CEN and REN
Table 7. Truth table X = Don't care High Z = High impedance output
11050CL
---- ------------
L6226Q Circuit description
Doc ID 14335 Rev 5 13/29
values and its magnitude is reported in Figure 12. The delay time tDELAY before turning off
the bridge when an overcurrent has been detected depends only by CEN value. Its
magnitude is reported in Figure 13.
CEN is also used for providing immunity to pin EN against fast transient noises. Therefore
the value of CEN should be chosen as big as possible according to the maximum tolerable
Delay Time and the REN value should be chosen according to the desired Disable Time.
The resistor REN should be chosen in the range from 2.2 kΩ to 180 kΩ. Recommended
values for REN and CEN are respectively 100 kΩ and 5.6 nF that allow obtaining 200 μs
disable time.
Figure 9. Overcurrent protection simplified schematic
14/29 Doc ID 14335 Rev 5
Figure 11. Output current protection threshold versus RCL
value
L6226Q Circuit description
Doc ID 14335 Rev 5 15/29
Figure 12. tDISABLE versus CEN and REN (VDD = 5 V)
Figure 13.t DELAY versus CEN (VDD = 5 V)
