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LC321664AJ-80 ,1MEG (65536words x 16bit) DRAM fast page mode, byte writeAbsolute Maximum RatingsParameter Symbol Ratings Unit NoteMaximum supply voltage V max –1.0 to +7.0 ..
LC321664AM-80 ,1MEG (65536words x 16bit) DRAM fast page mode, byte writeFeatures• 65536-word · 16-bit configurationSANYO:SOJ40• Single 5 V ±10% power supply• All input and ..
LC321664BJ ,1 MEG (65536 words X 16 bits) DRAM Fast Page Mode, Byte WriteFeatures. 65536 words M 16 bits configuration,. Single 5 V , 10% power supply.. All input and outpu ..
LC321664BJ-70 ,1 MEG (65536 words x 16 bit) DRAM, fast page mode, byte writeFeatures. 65536 words M 16 bits configuration,. Single 5 V , 10% power supply.. All input and outpu ..
LC321664BJ-80 ,1 MEG (65536 words x 16 bit) DRAM fast page mode, byte writeOrdering number : EN5082AOve rviewThe LC321664BJ, BM, BT is a CMOS dynamic RAMoperating on a single ..
L6223
DMOS PROGRAMMABLE HIGH SPEED UNIPOLAR STEPPER MOTOR DRIVER
BLOCK DIAGRAM
L6223DMOS PROGRAMMABLE
HIGH SPEED UNIPOLAR STEPPER MOTOR DRIVER
HIGH EFFICIENCY UNIPOLAR STEPPER
MOTOR DRIVER
HIGH SPEED UNIPOLAR STEPPER MOTOR
DRIVER
SUPPLY VOLTAGE UP TO 46V
PHASE CURRENT UP TO 1A
UP TO 2A/PHASE IN DUAL CONFIGURA-
TION
PARALLEL CMOS μP INTERFACE FOR
FULL/HALF STEP MOTOR ROTATION
SERIAL INTERFACE FOR 6 BIT PROGRAM-
MING
CLOSE/OPEN LOOP, 8 PWM CURRENT
LEVELS
DUAL PWM FREQUENCY SELECTION
INPUT BIDIRECTIONALLY PROTECTED
THERMAL SHUTDOWN
DESCRIPTIONThe L6223 is a programmable integrated system
for driving a unipolar stepper motor. It is realized
in Multipower BCD technology. The DMOS output
stage, realized by a single upper DMOS switch
and four lower DMOS, can deliver up to 1A/phase
with motor supply voltages up to 46V.
All inputs are CMOS and microprocessor compat-
ible. An internal 6-bit shift register allows the de-
vice to be programmed to select different duty cy-
cles in open loop mode and different chopping
frequencies in closed loop mode. When the cur-
rent control is in closed loop mode it is also possi-
ble to select a reduced current chopping level to
optimize system efficiency. The L6223 is de-
PIN CONNECTION ( top wiew )signed to work with a single sense resistor. Dur-
ing chopping t(OFF) time the current is reduced
by half, improving efficiency. Higher current appli-
cations can be achieved by paralleling two L6223.
The L6223 is mounted in a 20-lead Powerdip
package, (16+2+2). Four ground leads conduct
heat to dedicated heatsink area on the PCB.
( * ) Oscillator running
( ** ) 4 cm2 copper area on PCB, see fig. 34
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
L6223
PIN DESCRIPTION
L6223
ELECTRICAL CHARACTERISTICS (Tj = 25°C, VS = 42V, VSS = 5V, external RC network: R = 18kΩ, C = 3.3nF, unless otherwise specified).
SINK MOS
SOURCE MOS
CURRENT CONTROL SECTION
LOGIC LEVELS
L6223
ELECTRICAL CHARACTERISTICS (Continued)
SWITCHING TIMING
PROGRAMMING TIMINGNote 1) Upper DMOS turn ON delay when the signal is applied at the input comparator (point A in Fig. 4).
Note 2) Internal clock pulse is generated only if IN1...IN4 stay Low for almost 0.2 μs. This delay avoids undesirable programmings.
Figure 1: Output leakage IOL Test Circuit Figure 2a: Source Output DMOS RDS(ON) Test Circuit
L6223
