L6205D ,DUAL DMOS FULL BRIDGE MOTOR DRIVERL6205DMOS DUAL FULL BRIDGE DRIVER■ OPERATING SUPPLY VOLTAGE FROM 8 TO 52V■5.6A OUTPUT PEAK CURRENT ..
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L6205N ,DUAL DMOS FULL BRIDGE MOTOR DRIVERAPPLICATIONS■ BIPOLAR STEPPER MOTORBCD technology, which combines isolated DMOS■ DUAL OR QUAD DC MO ..
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L6205PD ,DUAL DMOS FULL BRIDGE MOTOR DRIVERapplications, realized in MultiPower-high side PowerMOSFETs and thermal shutdown.
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L6205D-L6205N-L6205PD
DUAL DMOS FULL BRIDGE MOTOR DRIVER
1/18
L6205April 2002 OPERATING SUPPLY VOLTAGE FROM 8 TO 52V 5.6A OUTPUT PEAK CURRENT (2.8A DC) RDS(ON) 0.3Ω TYP. VALUE @ Tj = 25 °C OPERATING FREQUENCY UP TO 100KHz NON DISSIPATIVE OVERCURRENT
PROTECTION PARALLELED OPERATION CROSS CONDUCTION PROTECTION THERMAL SHUTDOWN UNDER VOLTAGE LOCKOUT INTEGRATED FAST FREE WHEELING DIODES
TYPICAL APPLICATIONS BIPOLAR STEPPER MOTOR DUAL OR QUAD DC MOTOR
DESCRIPTIONThe L6205 is a DMOS Dual Full Bridge designed for
motor control applications, realized in MultiPower-
BCD technology, which combines isolated DMOS
Power Transistors with CMOS and bipolar circuits on
the same chip. Available in PowerDIP20 (16+2+2),
PowerSO20 and SO20(16+2+2) packages, the
L6205 features a non-dissipative protection of the
high side PowerMOSFETs and thermal shutdown.
BLOCK DIAGRAMDMOS DUAL FULL BRIDGE DRIVER
L6205 2/18
ABSOLUTE MAXIMUM RATINGS
RECOMMENDED OPERATING CONDITIONS
3/18
L6205
THERMAL DATA
PIN CONNECTIONS (Top View)<1> Mounted on a multilayer FR4 PCB with a dissipating copper surface on the bottom side of 6 cm2 (with a thickness of 35 μm).
<2> Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 μm).
<3> Mounted on a multilayer FR4 PCB with a dissipating copper surface on the top side of 6 cm2 (with a thickness of 35 μm), 16 via holes
and a ground layer.
<4> Mounted on a multilayer FR4 PCB without any heat sinking surface on the board.
L6205 4/18
(*) Also connected at the output drain of the Overcurrent and Thermal protection MOSFET. Therefore, it has to be driven putting in series a
resistor with a value in the range of 500Ω - 22KΩ, recommended 10kΩ
PIN DESCRIPTION
5/18
L6205
ELECTRICAL CHARACTERISTICS (Tamb = 25 °C, Vs = 48V, unless otherwise specified)
Output DMOS Transistors
Source Drain Diodes
Switching Characteristics
UVLO comp
Logic Input
L6205 6/18
<(5)> See Fig. 1.
Figure 1. Switching Characteristic Definition
Over Current Protection
ELECTRICAL CHARACTERISTICS (continued)(Tamb = 25 °C, Vs = 48V, unless otherwise specified)
7/18
L6205
CIRCUIT DESCRIPTION
POWER STAGES and CHARGE PUMPThe L6205 integrates two independent Power MOS
Full Bridges. Each Power MOS has an Rd-
son=0.3ohm (typical value @25°C), with intrinsic fast
freewheeling diode. Cross conduction protection is
achieved using a dead time (td = 1μs typical) be-
tween the switch off and switch on of two Power MOS
in one leg of a bridge.
Using N Channel Power MOS for the upper transis-
tors in the bridge requires a gate drive voltage above
the power supply voltage. The Bootstrapped (Vboot)
supply is obtained through an internal Oscillator and
few external components to realize a charge pump
circuit as shown in Figure 2. The oscillator output
(VCP) is a square wave at 750kHz (typical) with 10V
amplitude. Recommended values/part numbers for
the charge pump circuit are shown in Table1.
Table 1. Charge Pump External Components
Values
Figure 2. Charge Pump Circuit
LOGIC INPUTSPins IN1A, IN2A, IN1B and IN2B are TTL/CMOS and
μC compatible logic inputs. The internal structure is
shown in Fig. 3. Typical value for turn-on and turn-off
thresholds are respectively Vthon=1.8V and
Vthoff=1.3V.
Pins ENA and ENB have identical input structure with
the exception that the drains of the Overcurrent and
thermal protection MOSFETs (one for the Bridge A
and one for the Bridge B) are also connected to these
pins. Due to these connections some care needs to
be taken in driving these pins. The ENA and ENB in-
puts may be driven in one of two configurations as
shown in figures 4 or 5. If driven by an open drain
(collector) structure, a pull-up resistor REN and a ca-
pacitor CEN are connected as shown in Fig. 4. If the
driver is a standard Push-Pull structure the resistor
REN and the capacitor CEN are connected as shown
in Fig. 5. The resistor REN should be chosen in the
range from 500Ω to 22KΩ. Recommended values for
REN and CEN are respectively 10KΩ and 100nF.
More information on selecting the values is found in
the Overcurrent Protection section.
Figure 3. Logic Inputs Internal Structure
Figure 4. ENA and ENB Pins Open Collector
Driving
Figure 5. ENA and ENB Pins Push-Pull Driving
TRUTH TABLE = Don't care
High Z = High Impedance Output
L6205 8/18
NON-DISSIPATIVE OVERCURRENT PROTECTIONIn addition to the PWM current control, an overcurrent detection circuit (OCD) is integrated for full protection.
This circuit provides protection against a short circuit to ground or between two phases of the bridge. With this
internal over current detection, the external current sense resistor normally used and its associated power dis-
sipation are eliminated. Figure 6 shows a simplified schematic of the overcurrent detection circuit for the Bridge
A. Bridge B is provided of an analogous circuit.
To implement the over current detection, a sensing element that delivers a small but precise fraction of the out-
put current is implemented with each high side power MOS. Since this current is a small fraction of the output
current there is very little additional power dissipation. This current is compared with an internal reference cur-
rent IREF. When the output current reaches the detection threshold (typically 5.6A) the OCD comparator signals
a fault condition. When a fault condition is detected, the EN pin is pulled below the turn off threshold (1.3V typ-
ical) by an internal open drain MOS with a pull down capability of 4mA. By using an external R-C on the EN pin,
the off time before recovering normal operation can be easily programmed by means of the accurate thresholds
of the logic inputs. Figure 7 shows the OCD operation.
Figure 6. Overcurrent Protection Simplified Schematic
Figure 7. Overcurrent Protection Waveforms
9/18
L6205
APPLICATION INFORMATIONA typical application using L6205 is shown in Fig. 8. Typical component values for the application are shown in
Table 2. A high quality ceramic capacitor in the range of 100 to 200 nF should be placed between the power
pins (VSA and VSB) and ground near the L6205 to improve the high frequency filtering on the power supply and
reduce high frequency transients generated by the switching. The capacitors connected from the ENA and ENB
inputs to ground set the shut down time for the Brgidge A and Bridge B respectively when an over current is
detected (see Overcurrent Protection). The two current sources (SENSEA and SENSEB) should be connected
to Power Ground with a trace length as short as possible in the layout. To increase noise immunity, unused logic
pins (except ENA and ENB) are best connected to 5V (High Logic Level) or GND (Low Logic Level) (see pin
description). It is recommended to keep Power Ground, Signal Ground and Charge Pump Ground (low side of
CBOOT capacitor) separated on PCB.
Table 2. Component Values for Typical Application
Figure 8. Typical Application
