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L5993-L5993D
CONSTANT POWER CONTROLLER
L5993CONSTANT POWER CONTROLLER
CURRENT-MODE CONTROL PWM
SWITCHINGFREQUENCY UP TO 1MHz
LOW START-UP CURRENT(< 120μA)
CONSTANT OUTPUT POWER VS. SWITCH-
ING FREQUENCY
HIGH-CURRENT OUTPUT DRIVE SUITABLE
FOR POWER MOSFET (1A)
FULLY LATCHED PWM LOGIC WITH DOU-
BLE PULSE SUPPRESSION
PROGRAMMABLE DUTY CYCLE
100%AND 50% MAXIMUM DUTY CYCLELIMIT
PROGRAMMABLE SOFT START
PRIMARY OVERCURRENT FAULT DETEC-
TION WITH RE-START DELAY
PWM UVLO WITH HYSTERESIS
IN/OUT SYNCHRONIZATION
LATCHED DISABLE
INTERNAL 100ns LEADING EDGE BLANK-
ING OF CURRENT SENSE
PACKAGE: DIP16 ANDSO16N
DESCRIPTIONThis primary controller I.C., developedin BCD60II
technology, has been designedto implement off
lineor DC-DC power supply applications usinga
fixed frequencycurrent mode control.
Basedona standard current mode PWM control-
ler this device includes some features such as
programmable soft start, IN/OUT synchronization,
disable(tobe usedfor over voltage protection and
for power management), precise maximum Duty
Cycle Control, 100ns leading edge blanking on
current sense, pulseby pulse current limit, over-
current protection with soft start intervention and
”constant power” functionfor cotrolling throughput
powerin multisync monitor SMPS.
July 1999
TIMING214
Vref
CLK
2.5V1.2V
BLANKING
PWM
FAULT
SOFT-START
25V
15V/10V
VREFOK
DIS
E/A R
DIS
2.5V78151
13V
PWM UVLO
SGND COMP
ISEN
DIS
RCT
SYNC DC-LIM VCC VREF
D97IN765
VFB
PGND
OUT
OVERCURRENT16C-POWER
BLOCK DIAGRAM
ORDERING NUMBERS: L5993 (DIP16)
L5993D (SO16)
MULTIPOWER BCD TECHNOLOGY
DIP16 SO16N1/22
ABSOLUTEMAXIMUM RATINGS
Symbol Parameter Value UnitVCC Supply Voltage (ICC< 50mA)(*) selflimit V
IOUT Output Peak Pulse Current 1.5 A
Analog Inputs& Outputs (6,7) -0.3to8 V
Analog Inputs& Outputs (1,2,3,4,5,15,14,13, 16) -0.3to6 V
Ptot Power Dissipation@ Tamb =70°C (DIP16)
@Tamb =50°C (SO16)
0.83 Junction Temperature, Operating Range -40to 150 °C
Tstg Storage Temperature, Operating Range -55to 150 °C
(*) maximum package power dissipationlimitsmust beobserved
THERMAL DATA
Symbol Parameter Value UnitRthj-amb Thermal Resistance Junction -Ambient
(DIP16)Thermal Resistance Junction -Ambient
(SO16)°C/W
°C/W
PIN FUNCTIONS Name Function SYNC Synchronization.A synchronization pulse terminatesthe PWM cycle and dischargesCt RCT Oscillatorpinfor external Ct,Rt components DC Duty Cycle control VREF 5.0V +/-1.5% reference voltageat 25°C VFB Error Amplifier Inverting input COMP Error Amplifier Output SS Soft startpinfor external capacitor Css
8VCC Supplyfor internal ”Signal” circuitry
9VC Supplyfor Power section OUT High current totem pole output PGND Power ground SGND Signal ground ISEN Current sense DIS Disable.It must neverbe left floating.Tieto SGNDifnot used. DC-LIM Connecting thispinto Vref, DCis limitedto 50%.Ifitis left floatingor groundedno limitationis
imposed C-POWER Constant Powervs. Switching Frequency. Connecta capacitorto SGND. Thepin mustbe
connected toVREFifnot used.
SYNC
RCT
VREF
VFB
COMP OUT
SGND
PGND
ISEN
DIS
DC-LIM
C-POWER16
D97IN783
VCC 8VC9
PIN CONNECTION
L59932/22
ELECTRICAL CHARACTERISTICS (VCC= 15V;Tj=0to 105°C;RT= 13.3kΩ;CT= 1nF
unless otherwisespecified.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
REFERENCE SECTIONVRef Output Voltage Tj =25°C;IO= 1mA 4.925 5.0 5.075 V
Line Regulation VCC=12to 20V;Tj =25°C 2.0 10 mV
Load Regulation IO=1to 10mA;Tj =25°C 2.0 10 mV Temperature Stability 0.4 mV/°C
Total Variation Line, Load, Temperature 4.80 5.0 5.130 V
IOS Short Circuit Current Vref=0V 30 150 mA
Power Down/UVLO VCC= 8.5V; Isink= 0.5mA 0.2 0.5 V
OSCILLATOR SECTIONInitial Accuracy pin15= Vref Tj =25°C
VCC= 12to 20V
kHz
kHz
Duty Cycle pin3= 0,7V,pin15= Vref
pin3= 0.7V,pin15= OPEN
Duty Cycle pin3= 3.2V,pin15= Vref
pin3= 3.2V,pin15= OPEN
Duty Cycle Accuracy pin3= 2.79V,pin15= OPEN 75 80 85 %
Oscillator Ramp Peak 2.8 3.0 3.2 V
Oscillator Ramp Valley 0.75 0.9 1.05 V
ERROR AMPLIFIER SECTIONInput Bias Current VFBto GND 0.2 3.0 μA Input Voltage VCOMP =VFB 2.42 2.5 2.58 V
GOPL Open Loop Gain VCOMP= 2to4V 60 90 dB
SVR Supply Voltage Rejection VCC=12to 20V 85 dB
VOL Output Low Voltage Isink= 2mA, VFB= 2.7V 1.1 V
VOH Output High Voltage Isource= 0.5mA, VFB= 2.3V 5 6 V Output SourceCurrent VCOMP> 4V, VFB= 2.3V 0.5 1.3 2.5 mA
Output Sink Current VCOMP> 1.1V, VFB= 2.7V 2 6 mA
Unit Gain Bandwidth 1.7 4 MHz Slew Rate 8 V/μs
PWM CURRENT SENSE SECTION Input Bias Current Isen =0 3 15 μA Maximum Input Signal VCOMP=5V 0.92 1.0 1.08 V
Delayto Output 70 100 ns
Gain 2.85 3 3.15 V/V
SOFT STARTISSC SS Charge Current 14 20 26 μA
ISSD SS Discharge Current VSS= 0.6V,Tj =25°C 5 10 15 μA
VSSSAT SS Saturation Voltage DC= 0% 0.6 V
VSSCLAMP SS Clamp Voltage 7 V
LEADING EDGE BLANKINGInternal Masking Time 100 ns
OUTPUT SECTIONVOL Output Low Voltage IO= 250mA 1.0 V
VOH Output High Voltage IO= 20mA; VCC= 12V 10 10.5 V= 200mA; VCC= 12V 9 10 V
VOUT CLAMP Output Clamp Voltage IO= 5mA; VCC= 20V 13 V
L59933/22
ELECTRICAL CHARACTERISTICS (continued.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
OUTPUT SECTIONCollector Leakage VCC= 20V VC= 24V 2 20 μA
Fall Time CO= 1nF= 2.5nF ns
Rise Time CO= 1nF= 2.5nF
100 ns
UVLO Saturation VCC =0Vto VCCON;Isink= 10mA 1.0 V
SUPPLY SECTIONVCCON Startup voltage 14 15 16 V
VCCOFF Minimum Operating Voltage 9 10 11 V
Vhys ULVO Hysteresis 4.5 5 V StartUp Current Before Turn-onat:
VCC =VCCON- 0.5V 75 120 μA
Iop Operating Current CT= 1nF,RT= 13.3kΩ,CO
=1nF
913 mA Quiescent Current (After turn on), CT= 1nF,= 13.3kΩ,CO= 0nF
7.0 10 mA Zener Voltage I8= 20mA 21 25 30 V
SYNCHRONIZATION SECTION
Master Operation Clock Amplitude ISOURCE= 0.8mA 4 V Clock Source Current Vclock= 3.5V 3 7 mA
Slave Operation Sync Pulse Low Level 1 V
High Level 3.5 V Sync Pulse Current VSYNC= 3.5V 0.5 mA
OVER CURRENT PROTECTION Fault Threshold Voltage 1.1 1.2 1.3 V
DISABLE SECTIONShutdown threshold 2.4 2.5 2.6 V
ISH Shutdown Current VCC= 15V 330 μA
CONSTANT POWERV14=0, Pin2= open= 25°C 8 12 16 20 24
Vcc[V] [mA]
Figure1. Quiescent current vs. input voltage. 4 8 121620240
Vcc [V] [μA]
V14= Vref=25°C
Figure2. Quiescentcurrent vs. input voltage
(after disable).
L59934/22
1012 14161820 22 249.0c [V] [mA]
V14=0,V5= Vref= 4.5Kohm,Tj= 25°C
500Khz
300Khz
1Mhz
100Khz
Figure3. Quiescent current vs. input voltage. 5 10 15 20 25
Iref [mA]
Vref[V]
Vcc=15V= 25°C
Figure6. Reference voltage vs. load current.-50 -25 0 25 50 75 100 125 150
5.1 (°C)
Vref [V])
Vcc= 15V
Iref= 1mA
Figure7. Vref vs. junction temperature.-50 -25 0 25 50 75 100 125 150
5.1 (°C)
Vref[V]
Vcc= 15V
Iref= 20mA
Figure8. Vref vs. junction temperature. 1012 14 1618 2022
Vcc[V] [mA]= 1nF,Tj= 25°C= 100%
1MHz
500KHz
300KHz
100KHz
Figure5. Quiescent current vs. input voltage
and switching frequency. 10 12 1416 182022
Vcc[V] [mA]o= 1nF,Tj= 25°C=0%
1MHz 0KHz 0KHz 00KHz
Figure4. Quiescent current vs. input voltage
and switchingfrequency.
L59935/22
0.2 0.4 0.6 0.8 1 1.2Isource[A]
Vsat=V [V]
Vcc=Vc= 15V= 25°C
Figure 10. Output saturation. 0.2 0.4 0.6 0.8 1 1.2
Isink [A]Vsat=V [V]
Vcc=Vc= 15V= 25°C
Figure 11. Outputsaturation. 10 100 1000 10000
fsw (Hz)
SVRR (dB)
Vcc=15V
Vp-p=1V
Figure9. Vref SVRR vs. switching frequency.-50 -25 0 25 50 75 100 125 150
320 (°C)
fsw (KHz)
Rt= 4.5Kohm,Ct= 1nF
Vcc= 15V, V15=Vref
Figure 14. Switching frequency vs. tempera-
ture 200 400 600 800 1,000 1,200 1,4000
Vpin10 [mV]
Ipin10 [mA]
Vcc
beforeturn-on
Figure 12. UVLO Saturation 20 30 40
5000 (kohm)
fsw (KHz)
100pF
220pF
470pF
1nF2.2nF5.6nF= 25°C
Vcc= 15V,V15 =0V
Figure 13. Timing resistor vs. switching fre-
quency.
L5993
6/22
1020304050 60708090 100Duty Cycle [%] Control Voltage Vpin3[V]= 4.5Kohm,= 1nF
V15=0VV15= Vref
Figure 17. Maximum Duty Cyclevs Vpin3.
0.01 0.1 1 10 100 1000 10000 100000
f(KHz) [dB] Phase
Figure 19. E/A frequency response.
2468 10
1,200
1,500
TimingcapacitorCt [nF]
Dead time [ns] =4.5Kohm
V15 =0V
V15=Vref
Figure 16. Dead timevs Ct.
-50 -25 0 25 50 75 100 125 150
320 (°C)
fsw (KHz)
Rt= 4.5Kohm,Ct= 1nF
Vcc= 15V,V15=0
Figure 15. Switching frequencyvs. temperature.
-50 -25 0 25 50 75 100 125 15028 (°C)
Delayto output(ns)
PIN10= OPEN pulse PIN13
Figure 18. Delayto outputvs junction tem-
perature.
L5993
7/22
CONSTANT POWER FUNCTION
Pulse-by-pulse current limitation prevents peak
primary current from exceedinga given level.
This,in turn, limits the maximum power deliver-
ableto the output or,in other words, the power
capabilityofa converter. The capability, however,
depends on switching frequency: for example,in discontinuouscurrent mode flyback they are just
proportional. SMPS’of raster-scanned CRT displays the
switching frequencyis usually synchronizedto the
raster line scan signalof the displayin ordertoin-
crease noise immunity. More and more often,
CRT displays are requiredto operate withina
rangeof different video frequencies (e.g. from31
kHzto64 kHz), thus also the switching frequency theSMPS will varyin thatrange. caseof some failure, the power throughput may excessive without necessarily tripping the
pulse-by-pulsecurrent limitation circuit becauseof high operating frequency.
For the sakeof safety,it would be then desirable design the power stageofa converter (power
MOSFET, transformer, catch diode) so asto be
ableto withstand the maximum power throughput
under failure conditions. However, thisisa con-
siderable increaseof size and cost.
The ”Constant Power” functionof the L5993 al-
lows to overcome this problem. The device
changes the thresholdofits pulse-by-pulse cur-
rent limitation circuitso asto maintain fairly con-
stant the power capabilityofa flyback converter
despite the changesof the switching frequency.
Thisis accomplished by clamping the outputof
the error amplifier (VCOMP)toa value which de-
creasesas the frequencyof the signal fed into pin (SYNC)builds up.
The frequency-to-voltage conversion neededto
achieve this functionalityis performedby detect-
ing the peak voltageof the (synchronized) oscilla-
tor witha peak-holding circuit. One external ca-
pacitor onlyis required.is importantto point out that shape, amplitude
and durationof the synchronization pulses areof concern with this technique.
APPLICATION INFORMATION
Detailed Pin Functions Description
Pin1. SYNC (In/Out Synchronization). This func-
tion allows the IC’s oscillator eitherto synchronize
other controllers (master)ortobe synchronizedto externalfrequency (slave).a master, the pin delivers positive pulses dur-
ing the falling edgeof the oscillator (see pin2).In
slave operation the circuitis edge triggered. Refer fig. 21to see howit works. When severalIC
workin parallel no master-slave designationis
needed because the fastest one becomes auto-
matically the master.
During the ramp-upof the oscillator the pinis
pulled lowbya 600μA internal sink current gener-
ator. During the falling edge, thatis when the
pulseis released, the 600μA pull-downis discon-
nected. The pin becomesa generator whose
source capabilityis typically 7mA (witha voltage
still higher than 3.5V). fig. 20, some practical examplesof synchroniz-
ing the L5993 are given.
Pin2. RCT (Oscillator).A resistor (RT) anda ca-
pacitor (CT), connectedas shownin fig.21 set the
operating frequency foscof the oscillator.is charged throughRT untilits voltage reaches
3V, thenis quickly internally discharged. As the
voltage has droppedto 1Vit starts being charged
again.
The frequency can be established with the aidof
fig. 13 diagramsor considering the approximate
relationship:
fosc≅ 1⋅ (0.693⋅RT+ KT) (1)
whereKTis defined as:=
90, V15= VREF
160 V15= GND/OPEN (2)
andis linkedto the durationof the falling edgeof
the sawtooth:≅30⋅10-9 +KT⋅CT (3)is also the durationof the sync pulses deliv-
L5993 L5993
VREF
SYNCSYNC
RCTRCT
L4981A
(MASTER)
L5993
(SLAVE)
VREFSYNC
RCT
ROSC COSC CT
L5993
(MASTER)
L4981A
(SLAVE)
SYNC
ROSCCT COSC
SYNC
(a) (b) (c)
D97IN766B
VREF17 RCT 121718
Figure 20. Sinchronizingthe L5993.
L5993
8/22
eredat pin1 and defines the upper extremeof the
duty cycle range,Dx (see pin 15 for Dx definition
and calculation). case V15is connectedto VREF, however, the
switching frequencyof the system will bea half
fosc. theICistobe synchronizedtoan externaloscil-
lator, RT and CT should be selected fora fosc
lower than the master frequencyin any condition
(typically, 10-20%), dependingon the toleranceRT andCT.
Pin3. DC (Duty Cycle Control). By biasing this
pin witha voltage between1 and3Vitis possible set the maximum duty cycle between0 and the
upper extremeDx (see pin 15). Dmaxis the desired maximum duty cycle, the
voltageV3tobe appliedto pin3is: =5-2 (2-Dmax) (4)
Dmaxis determined by internal comparison be-
tween V3 and the oscillator ramp (see fig. 22),
thusin case the deviceis synchronizedtoan ex-
ternal frequency fext (and therefore the oscillator
amplitudeis reduced),(4) changes into:=5−4⋅ exp Dmax⋅CT⋅ fext
(5) voltage below 1V will inhibit the driver output
stage. This couldbe used fora not-latcheddevice
disable, for examplein caseof overvoltage pro-
tection (see application ideas). no limitation on the maximum duty cycleis re-
quired (i.e. DMAX =DX), the pin hastobe left float-
ing. An internal pull-up (see fig. 22) holds the volt-
age above 3V. Should the pin pickup noise (e.g.
during ESD tests),it can be connectedto VREF
througha 4.7kΩ resistor.
Pin4. VREF (Reference Voltage). The deviceis
provided with an accurate voltage reference
(5V±1.5%) ableto deliver some mAto an external
circuit. small film capacitor (0.1 μF typ.), connected
between this pin and SGND,is recommendedto
ensure the stabilityof the generator andto prevent
noisefrom affectingthe reference.
Before device turn-on, this pin hasa sink current
capabilityof 0.5mA.R3
CLAMP
50ΩQ
600μA
D97IN500B
VREF
RCT
SYNC
CLK2 1
Figure 21. Oscillator and synchronization internal schematic.
D97IN711A
VREF
RCT PWM LOGIC
23K
28K
3μA
Figure 22. Duty cycle control.
L5993
9/22
Pin5. VFB (Error Amplifier Inverting Input). The
feedback signalis appliedto this pin andis com-
paredto the E/A internal reference (2.5V). The
E/A output generates the control voltage which
fixes the duty cycle.
The E/A features high gain-bandwidth product,
which allowsto broaden the bandwidthof the
overall control loop, high slew-rate and current ca-
pability, which improvesits large signal behavior.
Usually the compensation network, which stabi-
lizes the overall control loop,is connected be-
tween this pin and COMP (pin6).
Pin6. COMP (Error Amplifier Output). Usually,
this pinis used for frequency compensation and
the relevant networkis connected between this
pin and VFB (pin 5). Compensation networks to-
wards ground are not possible since the L5993
E/Aisa voltage mode amplifier (low output im-
pedance). See application ideas for some exam-
pleof compensationtechniques.
Pin7. SS (Soft-Start).At device start-up,a ca-
pacitor (Css) connected between this pin and
SGND (pin 12)is chargedby an internal current
generator, ISSC, up to about 7V. During this
ramp, the E/A outputis clampedby the voltage
across Css itself and allowedto rise linearly, start-
ing from zero, upto the steady-state value im-
posedby the control loop. The maximum timein-
terval during which the E/Ais clamped, referredto soft-starttime,is approximately:
Tss≅3⋅ Rsense⋅ IQpk
ISSC ⋅ Css (6)
where Rsenseis the current sense resistor (see pin
13) and IQpkis the switch peak current (flowing
through Rsense), which depends on the output
load. Usually, CSSis selected fora TSSin the or-
derof milliseconds. mentioned before, the soft-start intervenes
alsoin caseof severe overloador short circuiton
the output. Referringto fig. 23, pulse-by-pulse
current limitationis somehow effectiveas longas
the ON-timeof the power switch canbe reduced
(fromAto B). After the minimum ON-timeis
reached (fromB onwards) the currentis outof
control. prevent this risk,a comparator trips an over-
current handling procedure, named ’hiccup’ mode
operation, whena voltage above 1.2V (pointC)is
detected on current sense input (ISEN, pin 13).
Basically, theICis turnedoff and then soft-started longas the fault conditionis detected.Asa re-
sult, the operating pointis moved abruptlyto D,
creatinga foldback effect. Fig.24 illustrates the
operation.
The oscillation frequency appearing on the soft-
VOUT
TON
D.C.M. C.C.M.
IQpk
TON(min)
1-2·IQpk
IQpk(max)
IOUTISHORT IOUT(max)D97IN495
Figure 23. Regulation characteristicand re-
lated quantities
Thic time
SHORTIOUT
ISEN
FAULT5V
0.5V
D98IN986
Figure 24. Hiccup mode operation.
L5993
10/22
start capacitorin caseof permanent fault, referredas ’hiccup” period,is approximatelygiven by:
Thic≅ 4.5⋅
ISSC+ 1
ISSD Css (7)
Since the system tries restarting each hiccup cy-
cle, thereis not any latchoff risk.
”Hiccup” keeps the systemin controlin caseof
short circuits but does not eliminate power com-
ponents overstress during pulse-by-pulse limita-
tion (fromAto C). Other external protection cir-
cuits are neededifa better controlof overloadsis
required.
Pin8. VCC (Controller Supply). This pin supplies
the signal partof the IC. The deviceis enabledas
VCC voltage exceeds the start threshold and
works as longas the voltageis above the UVLO
threshold. Otherwise the deviceis shut down and
the current consumption is extremely low
(<150μA). Thisis particularly useful for reducing
the consumptionof the start-up circuit(in the sim-
plest case, just one resistor), whichis oneof the
most significant contributionsto power losses
whena converteris lightly loaded. internal Zener limits the voltage on VCCto
25V. TheIC current consumption increases con-
siderablyif this limitis exceeded. small film capacitor between this pin and SGND
(pin 12), placedas closeas possibleto the IC,is
recommendedto filterhigh frequency noise.
Pin9. VC (Supplyof the Power Stage).It supplies
the driverof the external switch and therefore ab-
sorbsa pulsed current. Thusitis recommendedto
placea buffer capacitor (towards PGND, pin 11, close as possibleto the IC) ableto sustain
these current pulses andin orderto avoid them
inducing disturbances.
This pin can be connectedto the buffer capacitor
directlyor througha resistor,as shownin fig. 25, control separately the turn-on and turn-off
speedof the external switch, typicallya Power-
MOS.At turn-onthe gate resistanceisRg +Rg’,at
turn-offisRg only.
Pin 10. OUT (Driver Output). This pinis the out-
put of the driver stageof the external power
switch. Usually, this will bea PowerMOS, al-
though the driveris powerful enoughto drive
BJT’s (1.6A source,2A sink, peak).
The driveris madeupofa totem pole witha high-
side NPN Darlington anda low-side VDMOS, thus
thereis no needof an external diode clampto
prevent voltage from going below ground. An in-
ternal clamp limits the voltage deliveredto the
gateat 13V. Thusitis possibleto supply the
driver (Pin9) with higher voltages without any risk damagefor the gate oxideof the external MOS.
The clamp does not cause any additional in-
creaseof power dissipation inside the chip since
the current peakof the gate charge occurs when
the gate voltageis few volts and the clampis not
active. Besides, no current flows when the gate
voltageis 13V, steady state.
Under UVLO conditionsan internal circuit (shown fig.26) holds the pin lowin orderto ensure that
the external MOS cannot be turnedon acciden-
tally. The peculiarityof this circuitisits abilityto
mantain the same sink capability (typically, 20mA 1V) from VCC= 0Vupto the start-up threshold.
When the thresholdis exceeded and the L5993
starts operating,VREFOKis pulled high (referto fig.
26) and the circuitis disabled.is then possibleto omit the ”bleeder” resistor
(connected between the gate and the sourceof
the MOS) ordinarily usedto prevent undesired
switching-onof the external MOS because of
some leakage current.
Pin 11. PGND (Power Ground). The current loop
during the dischargeof the gateof the external
MOSis closed through this pin. This loop should as short as possibleto reduce EMI and run
separatelyfrom signal currents return.
OUT Rg
DRIVE&
CONTROL
13VVCC
Rg’
PGND
Rg(ON)=Rg+Rg’
Rg(OFF)=Rg
D97IN767
L5993
Figure 25. Turn-on and turn-offspeeds adjust-
ment SGND
OUT
VREFOK
D97IN538
Figure 26. Pull-Downof the outputin UVLO
L5993
11/22
