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L5991-L5991A-L5991A.-L5991AD-L5991D
PRIMARY CONTROLLER WITH STANDBY
L5991
L5991APRIMARY CONTROLLER WITH STANDBY
CURRENT-MODE CONTROL PWM
SWITCHING FREQUENCY UP TO 1MHz
LOW START-UP CURRENT (< 120μA)
HIGH-CURRENT OUTPUT DRIVE SUITABLE
FOR POWER MOSFET (1A)
FULLY LATCHED PWM LOGIC WITH DOU-
BLE PULSE SUPPRESSION
PROGRAMMABLE DUTY CYCLE
100% AND 50% MAXIMUM DUTY CYCLE LIMIT
STANDBY FUNCTION
PROGRAMMABLE SOFT START
PRIMARY OVERCURRENT FAULT DETEC-
TION WITH RE-START DELAY
PWM UVLO WITH HYSTERESIS
IN/OUT SYNCHRONIZATION
LATCHED DISABLE
INTERNAL 100ns LEADING EDGE BLANK-
ING OF CURRENT SENSE
PACKAGE: DIP16 AND SO16
DESCRIPTIONThis primary controller I.C., developed in BCD60II
technology, has been designed to implement off
line or DC-DC power supply applications using a
fixed frequency current mode control.
Based on a standard current mode PWM control-
ler this device includes some features such as
programmable soft start, IN/OUT synchronization,
disable (to be used for over voltage protection and
for power management), precise maximum Duty
Cycle Control, 100ns leading edge blanking on
current sense, pulse by pulse current limit, over-
current protection with soft start intervention, and
Standby function for oscillator frequency reduction
when the converter is lightly loaded.
BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS(*) maximum package power dissipation limits must be observed
THERMAL DATA
PIN FUNCTIONS
PIN CONNECTION
L5991 - L5991A
ELECTRICAL CHARACTERISTICS (VCC = 15V; Tj = 0 to 105°C; RT = 13.3kΩ (*) CT = 1nF;unless otherwise specified.)
(*) RT = RA//RB, RA = RB = 27kΩ, see Fig. 23.
L5991 - L5991A
8 12 16 20 24Iq [mA]
Figure 1. L5991 - Quiescent current vs. input
voltage.
(X = 7.6V and Y= 8.4V for L5991A) 4 8 12 16 20 240
350c [V] [μA]
Figure 2. L5991 - Quiescent current vs. input
voltage (after disable).
(X = 7.6V and Y= 8.4V for L5991A)
ELECTRICAL CHARACTERISTICS (continued.)
L5991 - L5991A
10 1214 1618 202224 Vcc [V]
Iq [mA]
Figure 3. Quiescent current vs. input voltage. 5 10 15 20 25
Iref [mA]
Vref [V]
Figure 7. Reference voltage vs. load current.
Figure 8. Vref vs. junction temperature. 1012 1416182022
Vcc [V]
Iq [mA]
Figure 4. Quiescent current vs. input voltage
and switching frequency. 10 121416 1820 22
Vcc [V]
Iq [mA]
Figure 5. Quiescent current vs. input voltage
and switching frequency.-50 -25 0 25 50 75 100 125 150
Junction temperature [˚C]
[mA]
Figure 6. IC Consumption vs. Temperature.
L5991 - L5991A
0.2 0.4 0.6 0.8 1 1.2Isource [A]
Vsat = V [V]
Figure 11. Output saturation. 0.2 0.4 0.6 0.8 1 1.20
Isink [A] Vsat = V [V]
Figure 12. Output saturation. 10 100 1000 10000
fsw (Hz)
SVRR (dB)
Figure 10. Vref SVRR vs. switching frequency. 200 400 600 800 1,000 1,200 1,4000
Vpin10 [mV]
Ipin10 [mA]
Figure 13. UVLO Saturation 20 30 40
Rt (kohm)
fsw (KHz)
Figure 14. Timing resistor vs. switching frequency.-50 -25 0 25 50 75 100 125 150
Tj (°C)
Vref [V]
Figure 9. Vref vs. junction temperature.
L5991 - L5991A
0.01 0.1 1 10 100 1000 10000 100000
f (KHz)
G [dB] Phase
Figure 20. E/A frequency response.-50 -25 0 25 50 75 100 125 15028
Figure 19. Delay to output vs junction temperature.-50 -25 0 25 50 75 100 125 150
Tj (°C)
fsw (KHz)
Figure 16. Switching frequency vs. temperature.2468 10
1,200
1,500
Timing capacitor Ct [nF]
Dead time [ns]
Figure 17. Dead time vs Ct. 1020 3040 5060 7080 90 100
Duty Cycle [%]
DC Control Voltage Vpin3 [V]
Figure 18. Maximum Duty Cycle vs Vpin3.-50 -25 0 25 50 75 100 125 150
Tj (°C)
fsw (KHz)
Figure 15. Switching frequency vs. tempera-
ture.
L5991 - L5991A
STANDBY FUNCTIONThe standby function, optimized for flyback topol-
ogy, automatically detects a light load condition
for the converter and decreases the oscillator fre-
quency on that occurrence. The normal oscillation
frequency is automatically resumed when the out-
put load builds up and exceeds a defined thresh-
old.
This function allows to minimize power losses re-
lated to switching frequency, which represent the
majority of losses in a lightly loaded flyback, with-
out giving up the advantages of a higher switching
frequency at heavy load.
This is accomplished by monitoring the output of
the Error Amplifier (VCOMP) that depends linearly
on the peak primary current, except for an offset.
If the the peak primary current decreases (as a re-
sult of a decrease of the power demanded by the
load) and VCOMP falls below a fixed threshold
(VT1), the oscillator frequency will be set to a
lower value (fSB). When the peak primary current
increases and VCOMP exceeds a second threshold
(VT2) the oscillator frequency is set to the normal
value (fosc). An appropriate hysteresis (VT2-VT1)
prevents undesired frequency change when
power is such that VCOMP moves close to the
threshold. This operation is shown in fig. 21.
Both the normal and the standby frequency are
externally programmable. VT1 and VT2 are inter-
nally fixed but it is possible to adjust the thresh-
olds in terms of input power level.
APPLICATION INFORMATION
Detailed Pin Function Description
Pin 1. SYNC (In/Out Synchronization). This func-tion allows the IC’s oscillator either to synchronize
other controllers (master) or to be synchronized to
an external frequency (slave).
As a master, the pin delivers positive pulses dur-
ing the falling edge of the oscillator (see pin 2). In
slave operation the circuit is edge triggered. Refer
to fig. 23 to see how it works. When several IC
work in parallel no master-slave designation is
needed because the fastest one becomes auto-
matically the master.
During the ramp-up of the oscillator the pin is
pulled low by a 600μA internal sink current gener-
ator. During the falling edge, that is when the
pulse is released, the 600μA pull-down is discon-
nected. The pin becomes a generator whose
source capability is typically 7mA (with a voltage
still higher than 3.5V).
In fig. 22, some practical examples of synchroniz-
ing the L5991 are given.
Since the device automatically diminishes its op-
erating frequency under light load conditions, it is
reasonable to suppose that synchronization will
refer to normal operation and not to standby.
Pin 2. RCT (Oscillator). Two resistors (RA and RB)and one capacitor (CT), connected as shown in
fig. 23, allow to set separately the operating fre-
quency of the oscillator in normal operation (fosc)
and in standby mode (fSB).
CT is charged from Vref through RA and RB in nor-
mal operation (STANDBY = HIGH), through RA
only in standby ( STANDBY = LOW). See pin 16
description to see how the STANDBY signal is gen-
erated.
When the voltage on CT reaches 3V, the capaci-
tor is quickly internally discharged. As the voltage
has dropped to 1V it starts being charged again.
VCOMP
Pin
VT1
PNO
PSB
VT2
Figure 21. Standby dynamic operation.
Figure 22. Synchronizing the L5991.
L5991 - L5991A
The oscillation frequency can be established with
the aid of the diagrams of fig. 14, where RT will be
intended as the parallel of RA and RB in normal
operation and RT = RA in standby, or considering
the following approximate relationships:
fosc ≅ 1
CT ⋅ (0.693 ⋅ (RA // RB) + KT (1),
which gives the normal operating frequency, and:
fSB ≅ 1
CT ⋅ (0.693 ⋅ RA + KT) (2),
which gives the standby frequency, that is the one
the converter will operate at when lightly loaded.
In the above expressions, RA // RB means:
RA//RB = RA ⋅ RB
RA + RB,
while KT is defined as:
KT =
90 V15 = VREF
160 V15 = GND/OPEN (3),
and is related to the duration of the falling-edge of
the sawtooth:
Td ≈ 30 ⋅ 10−9 + KT ⋅ CT (4).
Td is also the duration of the sync pulses deliv-
ered at pin 1 and defines the upper extreme of the
duty cycle range, Dx (see pin 15 for DX definition
and calculation) since the output is held low dur-
ing the falling edge.
In case V15 is connected to VREF, however, the
from fig. 14 or resulting from (1) and (2).
To prevent the oscillator frequency from switching
back and forth from fosc to fSB, the ratio fosc / fSB
must not exceed 5.5.
If during normal operation the IC is to be synchro-
nized to an external oscillator, RA, RB and CT
should be selected for a fosc lower than the master
frequency in any condition (typically, 10-20% ),
depending also on the tolerance of the parts.
Pin 3. DC (Duty Cycle Control). By biasing this
pin with a voltage between 1 and 3 V it is possible
to set the maximum duty cycle between 0 and the
upper extreme Dx (see pin 15).
If Dmax is the desired maximum duty cycle, the
voltage V3 to be applied to pin 3 is:
V3 = 5 - 2 (2-Dmax) (5)
Dmax is determined by internal comparison be-
tween V3 and the oscillator ramp (see fig. 24),
thus in case the device is synchronized to an ex-
ternal frequency fext (and therefore the oscillator
amplitude is reduced), (5) changes into:
V3 = 5 − 4 ⋅ exp
− Dmax
RT ⋅ CT ⋅ fext
(6)
A voltage below 1V will inhibit the driver output
stage. This could be used for a not-latched device
disable, for example in case of overvoltage pro-
tection (see application ideas).
If no limitation on the maximum duty cycle is re-
quired (i.e. DMAX = DX), the pin has to be left float-
ing. An internal pull-up (see fig. 24) holds the volt-
age above 3V. Should the pin pick up noise (e.g.
Figure 23. Oscillator and synchronization internal schematic.
L5991 - L5991A
during ESD tests), it can be connected to VREF
through a 4.7kΩ resistor.
Pin 4. VREF (Reference Voltage). The device isprovided with an accurate voltage reference
(5V±1.5%) able to deliver some mA to an external
circuit.
A small film capacitor (0.1 μF typ.), connected
between this pin and SGND, is recommended to
ensure the stability of the generator and to prevent
noise from affecting the reference.
Before device turn-on, this pin has a sink current ca-
pability of 0.5mA.
Pin 5. VFB (Error Amplifier Inverting Input). Thefeedback signal is applied to this pin and is com-
pared to the E/A internal reference (2.5V). The
E/A output generates the control voltage which
fixes the duty cycle.
The E/A features high gain-bandwidth product,
which allows to broaden the bandwidth of the
overall control loop, high slew-rate and current ca-
pability, which improves its large signal behavior.
Usually the compensation network, which stabi-
lizes the overall control loop, is connected be-
tween this pin and COMP (pin 6).
Pin 6. COMP (Error Amplifier Output). Usually,
this pin is used for frequency compensation and
the relevant network is connected between this
pin and VFB (pin 5). Compensation networks to-
wards ground are not possible since the L5991
E/A is a voltage mode amplifier (low output im-
pedance). See application ideas for some exam-
ple of compensation techniques.
It is worth mentioning that the calculation of the
part values of the compensation network must
take the standby frequency operation into ac-
count. In particular, this means that the open-loop
crossover frequency must not exceed fSB/4 ÷
fSB/5.
The voltage on pin 6 is monitored in order to re-
duce the oscillator frequency when the converter
is lightly loaded (standby).
Pin 7. SS (Soft-Start). At device start-up, a ca-
pacitor (Css) connected between this pin and
SGND (pin 12) is charged by an internal current
generator, ISSC, up to about 7V. During this
ramp, the E/A output is clamped by the voltage
across Css itself and allowed to rise linearly, start-
ing from zero, up to the steady-state value im-
posed by the control loop. The maximum time in-
terval during which the E/A is clamped, referred to
as soft-start time, is approximately:
Tss ≅ 3 ⋅ Rsense ⋅ IQpk
ISSC ⋅ Css (7)
where Rsense is the current sense resistor (see pin
13) and IQpk is the switch peak current (flowing
through Rsense), which depends on the output
load. Usually, CSS is selected for a TSS in the or-
der of milliseconds.
As mentioned before, the soft-start intervenes
also in case of severe overload or short circuit on
the output. Referring to fig. 25, pulse-by-pulse
current limitation is somehow effective as long as
the ON-time of the power switch can be reduced
(from A to B). After the minimum ON-time is
reached (from B onwards) the current is out of
control.
To prevent this risk, a comparator trips an over-
current handling procedure, named ’hiccup’ mode
operation, when a voltage above 1.2V (point C) is
detected on current sense input (ISEN, pin 13).
Basically, the IC is turned off and then soft-started
as long as the fault condition is detected. As a re-
sult, the operating point is moved abruptly to D,
creating a foldback effect. Fig. 26 illustrates the
operation.
The oscillation frequency appearing on the soft-
start capacitor in case of permanent fault, referred
to as ’hiccup" period, is approximately given by:
Thic ≅ 4.5 ⋅
ISSC + 1
ISSD
⋅ Css (8)
Figure 24. Duty cycle control.
Figure 25. Regulation characteristic and re-
lated quantities.
L5991 - L5991A
Since the system tries restarting each hiccup cy-
cle, there is not any latchoff risk.
"Hiccup" keeps the system in control in case of
short circuits but does not eliminate power com-
ponents overstress during pulse-by-pulse limita-
tion (from A to C). Other external protection cir-
cuits are needed if a better control of overloads is
required.
Pin 8. VCC (Controller Supply). This pin suppliesthe signal part of the IC. The device is enabled as
VCC voltage exceeds the start threshold and
works as long as the voltage is above the UVLO
threshold. Otherwise the device is shut down and
the current consumption is extremely low
(<150μA). This is particularly useful for reducing
the consumption of the start-up circuit (in the sim-
plest case, just one resistor), which is one of the
most significant contributions to power losses in
standby.
An internal Zener limits the voltage on VCC to
25V. The IC current consumption increases con-
siderably if this limit is exceeded.
A small film capacitor between this pin and SGND
(pin 12), placed as close as possible to the IC, is
recommended to filter high frequency noise.
Pin 9. VC (Supply of the Power Stage). It suppliesthe driver of the external switch and therefore ab-
sorbs a pulsed current. Thus it is recommended to
place a buffer capacitor (towards PGND, pin 11,
as close as possible to the IC) able to sustain
these current pulses and in order to avoid them
inducing disturbances.
This pin can be connected to the buffer capacitor
directly or through a resistor, as shown in fig. 27,
to control separately the turn-on and turn-off
speed of the external switch, typically a Power-
MOS. At turn-on the gate resistance is Rg + Rg’, at
turn-off is Rg only.
Pin 10. OUT (Driver Output). This pin is the out-
put of the driver stage of the external power
switch. Usually, this will be a PowerMOS, al-
though the driver is powerful enough to drive
BJT’s (1.6A source, 2A sink, peak).
The driver is made up of a totem pole with a high-
side NPN Darlington and a low-side VDMOS, thus
there is no need of an external diode clamp to
prevent voltage from going below ground. An in-
ternal clamp limits the voltage delivered to the
gate at 13V. Thus it is possible to supply the
driver (Pin 9) with higher voltages without any risk
of damage for the gate oxide of the external MOS.
The clamp does not cause any additional in-
crease of power dissipation inside the chip since
the current peak of the gate charge occurs when
the gate voltage is few volts and the clamp is not
active. Besides, no current flows when the gate
voltage is 13V, steady state.
Under UVLO conditions an internal circuit (shown
Figure 26. Hiccup mode operation.
Figure 27. Turn-on and turn-off speeds adjust-
ment.
L5991 - L5991A
in fig.28) holds the pin low in order to ensure that
the external MOS cannot be turned on acciden-
tally. The peculiarity of this circuit is its ability to
mantain the same sink capability (typically, 20mA
@ 1V) from VCC = 0V up to the start-up threshold.
When the threshold is exceeded and the L5991
starts operating, VREFOK is pulled high (refer to fig.
28) and the circuit is disabled.
It is then possible to omit the "bleeder" resistor
(connected between the gate and the source of
the MOS) ordinarily used to prevent undesired
switching-on of the external MOS because of
some leakage current.
Pin 11. PGND (Power Ground). The current loopduring the discharge of the gate of the external
MOS is closed through this pin. This loop should
be as short as possible to reduce EMI and run
separately from signal currents return.
Pin 12. SGND (Signal Ground). This ground refer-ences the control circuitry of the IC, so all the
ground connections of the external parts related
to control functions must lead to this pin. In laying
out the PCB, care must be taken in preventing
switched high currents from flowing through the
SGND path.
Pin 13. ISEN (Current Sense). This pin is to beconnected to the "hot" lead of the current sense
resistor Rsense (being the other one grounded), to
get a voltage ramp which is an image of the cur-
rent of the switch (IQ). When this voltage is equal
to:
V13pk = IQpk ⋅ Rsense = VCOMP − 1.4 (9)
the conduction of the switch is terminated.
To increase the noise immunity, a "Leading Edge
Blanking" of about 100ns is internally realized as
shown in fig. 29. Because of that, the smoothing
RC filter between this pin and Rsense could be re-
moved or, at least, considerably reduced.
Pin 14. DIS (Device Disable). When the voltageon pin 14 rises above 2.5V the IC is shut down
and it is necessary to pull VCC (IC supply voltage,
pin 8) below the UVLO threshold to allow the de-
vice to restart.
The pin can be driven by an external logic signal
in case of power management, as shown in fig.
30. It is also possible to realize an overvoltage
protection, as shown in the section " Application
Ideas".If used, bypass this pin to ground with a fil-
ter capacitor to avoid spurious activation due to
noise spikes. If not, it must be connected to
SGND.
Pin 15. DC-LIM (Maximum Duty Cycle Limit). Theupper extreme, Dx, of the duty cycle range de-
pends on the voltage applied to this pin. Approxi-
mately,
Dx ≅ RT
RT + 230 (10)
if DC-LIM is grounded or left floating. Instead,
Figure 29. Internal LEB.
Figure 28. Pull-Down of the output in UVLO.
L5991 - L5991A
