L5973ADTR ,2A SWITCH STEP DOWN SWITCHING REGULATORElectrical Characteristics (T = 25°C, V = 12V, unless otherwise specified.)j CCSymbol Parameter Tes ..
L5973ADTR ,2A SWITCH STEP DOWN SWITCHING REGULATORFEATURESFigure 1. Package■ 2A INTERNAL SWITCH■ OPERATING INPUT VOLTAGE FROM 4.4V TO 36V■ 3.3V / (±2 ..
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L5973A-L5973AD-L5973ADTR
2A SWITCH STEP DOWN SWITCHING REGULATOR
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L5973ADDecember 2004
GENERAL FEATURES 2A INTERNAL SWITCH OPERATING INPUT VOLTAGE FROM 4.4V TO 36V 3.3V / (±2%) REFERENCE VOLTAGE OUTPUT VOLTAGE ADJUSTABLE FROM
1.235V TO 35V LOW DROPOUT OPERATION: 100% DUTY
CYCLE 500KHz INTERNALLY FIXED FREQUENCY VOLTAGE FEEDFORWARD ZERO LOAD CURRENT OPERATION INTERNAL CURRENT LIMITING INHIBIT FOR ZERO CURRENT
CONSUMPTION SYNCHRONIZATION PROTECTION AGAINST FEEDBACK
DISCONNECTION THERMAL SHUTDOWN
1.1 APPLICATIONS: CONSUMER: STB, DVD, TV, VCR,CAR
RADIO, LCD MONITORS NETWORKING: XDSL, MODEMS,DC-DC
MODULES COMPUTER: PRINTERS, AUDIO/GRAPHIC
CARDS, OPTICAL STORAGE, HARD DISK
DRIVE INDUSTRIAL: CHARGERS, CAR BATTERY
DC-DC CONVERTERS
DESCRIPTIONThe L5973AD is a step down monolithic power
switching regulator with a switch current limit of 2A so
it is able to deliver more than 1.5A DC current to the
load depending on the application conditions.
The output voltage can be set from 1.235V to 35V.
The high current level is also achieved thanks to an
SO8 package with exposed frame, that allows to re-
duce the Rth(j-amb) down to approximately 40°C/W
The device uses an internal P-Channel D-MOS tran-
sistor (with a typical of 200mΩ) as switching element
to avoid the use of bootstrap capacitor and guarantee
high efficiency.
An internal oscillator fixes the switching frequency at
500KHz to minimize the size of external components.
Having a minimum input voltage of 4.4V only, it is
particularly suitable for 5V bus, available in all com-
puter related applications.
Pulse by pulse current limit with the internal frequen-
cy modulation offers an effective constant current
short circuit protection.
2A SWITCH STEP DOWN SWITCHING REGULATOR
Figure 2. Test and Application CircuitRev. 3
L5973AD
Table 2. Thermal Data(*) Package mounted on board
Figure 3. Pin Connection (top view)
Table 3. Pin Description
Table 4. Absolute Maximum Ratings
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L5973AD
Table 5. Electrical Characteristics (Tj = 25°C, VCC = 12V, unless otherwise specified.)Note:1. Guaranteed by design
L5973AD FUNCTIONAL DESCRIPTIONThe main internal blocks are shown in Fig. 1, where is reported the device block diagram. They are: A voltage regulator that supplies the internal circuitry. From this regulator, a 3.3V reference
voltage is externally available. A voltage monitor circuit that checks the input and internal voltages. A fully integrated sawtooth oscillator whose frequency is500KHz Two embedded current limitations circuitries which control the current that flows through the
power switch. The Pulse by Pulse Current Limit forces the power switch OFF cycle by cycle
if the current reaches an internal threshold, while the Frequency Shifter reduces the switch-
ing frequency in order to strongly reduce the duty cycle. A transconductance error amplifier. A pulse width modulator (PWM) comparator and the relative logic circuitry necessary to drive
the internal power. An high side driver for the internal P-MOS switch. An inhibit block for stand-by operation. A circuit to realize the thermal protection function.
Figure 4. Block Diagram
3.1 POWER SUPPLY & VOLTAGE REFERENCEThe internal regulator circuit (shown in Figure 2) consists of a start-up circuit, an internal voltage Prereg-
ulator, the Bandgap voltage reference and the Bias block that provides current to all the blocks.
The Starter gives the start-up currents to the whole device when the input voltage goes high and the de-
vice is enabled (inhibit pin connected to ground).
The Preregulator block supplies the Bandgap cell with a preregulated voltage VREG that has a very low
supply voltage noise sensitivity.
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L5973AD
3.2 VOLTAGES MONITORAn internal block senses continuously the Vcc, Vref and Vbg. If the voltages go higher than their thresholds, the
regulator starts to work. There is also an hysteresis on the VCC (UVLO).
Figure 5. Internal Regulator Circuit
3.3 OSCILLATOR & SYNCHRONIZATORFigure 6 shows the block diagram of the oscillator circuit.
The Clock Generator provides the switching frequency of the device that is internally fixed at 500KHz. The frequency
shifter block acts reducing the switching frequency in case of strong overcurrent or short circuit. The clock signal is
then used in the internal logic circuitry and is the input of the Ramp Generator and Synchronizator blocks.
The Ramp Generator circuit provides the sawtooth signal, used to realize the PWM control and the internal volt-
age feed forward, while the Synchronizator circuit generates the synchronization signal. Infact the device has a
synchronization pin that can works both as Master and Slave.
As Master to synchronize external devices to the internal switching frequency.
As Slave to synchronize itself by external signal.
In particular, connecting together two devices, the one with the lower switching frequency works as Slave and
the other one works as Master.
To synchronize the device, the SYNC pin has to pass from a low level to a level higher than the synchronization
threshold with a duty cycle that can vary approximately from 10% to 90%, depending also on the signal frequen-
cy and amplitude.
The frequency of the synchronization signal must be at least higher than the internal switching frequency of the
device (500KHz).
L5973AD
Figure 6. Oscillator Circuit
3.4 CURRENT PROTECTIONThe L5973AD has two current limit protections, pulse by pulse and frequency fold back.
The schematic of the current limitation circuitry for the pulse by pulse protection is shown in figure 7.
The output power PDMOS transistor is split in two parallel PDMOS. The smallest one has a resistor in series,
RSENSE. The current is sensed through Rsense and if reaches the threshold, the mirror is unbalanced and the
PDMOS is switched off until the next falling edge of the internal clock pulse.
Due to this reduction of the ON time, the output voltage decreases.
Since the minimum switch ON time (necessary to avoid false overcurrent signal) is not enough to obtain a suf-
ficiently low duty cycle at 500KHz, the output current, in strong overcurrent or short circuit conditions, could in-
crease again. For this reason the switching frequency is also reduced, so keeping the inductor current under its
maximum threshold. The Frequency Shifter (see fig. 6) depends on the feedback voltage. As the feedback volt-
age decreases (due to the reduced duty cycle), the switching frequency decreases too.
Figure 7. Current Limitation Circuitry
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L5973AD
3.5 ERROR AMPLIFIERThe voltage error amplifier is the core of the loop regulation. It is a transconductance operational amplifier whose
non inverting input is connected to the internal voltage reference (1.235V), while the inverting input (FB) is con-
nected to the external divider or directly to the output voltage. The output (COMP) is connected to the external
compensation network.
The uncompensated error amplifier has the following characteristics:
The error amplifier output is compared with the oscillator sawtooth to perform PWM control.
3.6 PWM COMPARATOR AND POWER STAGEThis block compares the oscillator sawtooth and the error amplifier output signals generating the PWM
signal for the driving stage.
The power stage is a very critical block cause it has to guarantee a correct turn on and turn off of the PD-
MOS.
The turn on of the power element, or better, the rise time of the current at turn on, is a very critical param-
eter to compromise.
At a first approach, it looks like the faster it is the rise time, the lower are the turn on losses.
But there is a limit introduced by the recovery time of the recirculation diode.
In fact when the current of the power element equals the inductor current, the diode turns off and the drain
of the power is free to go high. But during its recovery time, the diode can be considered as an high value
capacitor and this produces a very high peak current, responsible of many problems:
Spikes on the device supply voltage that cause oscillations (and thus noise) due to the board parasitics.
Turn on overcurrent causing a decrease of the efficiency and system reliability.
Big EMI problems.
Shorter freewheeling diode life.
The fall time of the current during the turn off is also critical. In fact it produces voltage spikes (due to the
parasitics elements of the board) that increase the voltage drop across the PDMOS.
In order to minimize all these problems, a new topology of driving circuit has been used and its block dia-
gram is shown in fig. 8.
The basic idea is to change the current levels used to turn on and off the power switch, according with the
PDMOS status and with the gate clamp status.
This circuitry allow to turn off and on quickly the power switch and to manage the above question related
to the freewheeling diode recovery time problem. The gate clamp is necessary to avoid that Vgs of the
internal switch goes higher than Vgsmax. The ON/OFF Control block avoids any cross conduction be-
tween the supply line and ground.
