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L5951
TRIPLE OUTPUT MULTIFUNCTION VOLTAGE REGULATOR FOR CAR RADIO WITH IDR/CLASS 2 INTERFACE
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L5951January 2001 3 VOLTAGE REGULATORS:
3.3V (100mA) STANDBY REGULATOR
5V (100mA) STANDBY REGULATOR
7.8V (100mA) OUT OF REGULATION DETECTION FOR 5V-
STANDBY REGULATOR WIDE OPERATING SUPPLY VOLTAGE
RANGE FROM 4.5V UP TO 26.5V FOR
TRANSIENT 34V VERY LOW STANDBY QUIESCENT
CURRENT (<150μA) INPUT TO OUTPUT SIGNAL TRANSFER
FUNCTION PROGRAMMABLE LVS FUNCTION TTL AND CMOS COMPATIBLE INPUTS OUTPUT CURRENT LIMITATION CONTROLLED OUTPUT SLOPE FOR LOW
EMI OVERTEMPERATURE SHUT-DOWN ABLE TO SURVIVE UNDER LOSS OF
GROUND OR BATTERY ESD PROTECTED
DESCRIPTIONThe L5951 is a monolithic triple regulator integrated
with a SAE J1850 Integrated Driver / Receiver real-
ized in advanced Multipower-BCD technology. It is
intended to drive single wire J1850 communications,
and offer microcontroller power and power manage-
ment for automotive or industrial applications.
TRIPLE OUTPUT MULTIFUNCTION VOLTAGE REGULATOR
FOR CAR RADIO WITH IDR/CLASS 2 INTERFACE
BLOCK DIAGRAM
L5951 2/13
FUNCTIONAL DESCRIPTION
1.1 General FeaturesThe L5951 is an integrated circuit which provides a J1850 physical layer as well three voltage regulators. The
L5951 was developed to provide the power and Class 2/IDR interface for a microcontroller.
1.2 REG1 Output VoltageThe REG1 regulator output is equal to 3.3V. The 3.3V regulator is non low drop out and can handle currents up
to 100mA with short citcuit limit of 280mA.
1.3 REG2 Output VoltageThe REG2 regulator output is equal to 5V and can handle currents up to 100mA with short citcuit limit of 280mA.
The output stage of the 5V regulator is low dropout.
1.4 REG3 Output VoltageThe REG3 regulator output is equal to 7.8V and can handle currents up to 100mA with short citcuit limit of
280mA. The output stage of the 7.8V regulator is low dropout. REG3 regulator is controlled by the EN (enable)
pin of the IC. REG3 can be turned on and off by toggling the EN pin. A logic "1" on the EN pin enables REG3,
while a logic "0" on the EN pin disables REG3. The maximum voltage when REG3 is off must be less than 0.2V.
Sleep* Input - The Class 2 transmitter can be turned on and turned off by the Sleep* pin. Once the voltage levelis above 2VDC, the transmitter is enabled. If the Sleep* pin drops below 0.8VDC, and EN is "0" the transceiver
goes into a low power mode. In low power mode, REG3 and the transceiver are disabled. The L5951 will still
receive messages and send them to the microcontroller out of the RX pin.
* denotes active low
LVS input - Reg1 and Reg2 are supplied by Vbat pin. The device could then dissipate a lot of power, causingthermal shutdown at high voltage. For this reason a secondary low voltage supply (LVS) can be used to reduce
power dissipation.
Reset* Output - The L5951 has low voltage or no voltage circuitry that is a warning to the microcontroller. IfREG2 drops 0.3VDC below its normal operating voltage, the Reset* pin will go to a logic "0". Between the volt-
age levels of 4.65VDC (min) and 5.10VDC (max) on REG2, a reset will occur. There is a hysterisis of 50mV on
the Reset* pin.
* denotes active low
Low Input Voltage Operation - If battery voltage level drops below 7.0V, the outputs are to remain alive andready for the return of normal voltage battery levels. The L5951 will be able to retrieve data off the BUS and
send it to the micrprocessor when the supply voltage is as low as 4.9V. The regulators should stay the same
voltage as the battery voltage down to 7.0V minus operating headroom for the 7.8V regulator. BUS VOH,min are
not guaranteed over all conditions below VBAT = 9.0V.
Waveshaping - Messages sent by the microcontroller to the transceiver are routed to a waveshaping circuit.The digital signal is rounded at the switching points in order to reduce EMI emissions. A second order function,
I = C*dV/dt, is used to control the rise and fall times of the transmission. The rise and fall times are controlled
by an external resistor Rext . The waveshaping circuit can be enabled and disabled by the 4X pin. A logic "1"
will disable the waveshape circuit and a logic "0" will enable the waveshape circuit. In 4X mode, the speed of
the BUS is increased by a factor of four. Any signal coming from the microcontroller and going to the BUS must
be waveshaped. If loopback(LOOP) is enabled, the signal coming from the micro through the TX pin is routed
to the RX pin back to the micro with or without it being waveshaped. A logic "1" enables loopback and a logic"0"
disables loopback.
Nodes - The transmitter provides a wave-shaped 0 to 7.7 VDC waveform on the BUS output. It also receiveswaveforms and transmits a digital level signal back to a logic IC. The transmitter can drive up to 32 remote trans-
ceivers. These remote nodes may be at ground potentials that are ±2 VDC, with respect to the assembly. Under
this condition, waveshaping will only be maintained during 3 of the 4 corners. The L5951 is a remote node on
the Class 2/IDR Bus. Each remote transceiver has a 470 + 10% pF capacitor on its output for EMI suppression,
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L5951as well as a 10.6 kW + 5% pull down resistor to ground. The main node has a 3,300 + 10% pF capacitor on its
output for EMI suppression, as well as a 1.5 kΩ + 5% pull down resistor to ground. With more than 26 nodes
there is no primary node , all nodes will have the 470 ±10% pF capacitor and the 10.6kΩ ±5% pull down resistor.
No matter how many remote nodes are on the Class 2/IDR Bus, the RC of the Class 2/IDR Bus is maintained
at approximately 5ms. The minimum and maximum load on the Class 2/IDR Bus is given below :
1.5 ProtectionThe L5951 can survive under the following conditions: shorting the outputs to BAT and GND, loss of BAT, loss
of IC GND, double battery(+26.5V), 4000V ESD, 34V load dump. L5951 will not handle a reverse battery con-
dition. External components must be implemented for reverse battery protection.
output and the Class 2 Bus Driver. V1 and V2 outputs shutdown at 160°C and returns to normal operation at
130°C. The V3 output and Class 2 Bus Driver shutdown at 150°C and return to normal operation at 120°C.
Current Limiting: each voltage regulator will contain its own current protection, and the maximum allowable cur-
rent for all three regulators is 280mA.
down will kick in. Current limiting will not disable the outputs.
but all other outputs will not operate.
1.6 Protocol DescriptionThe L5951 uses a Variable Pulse Width (VPW) modulated protocol. One frame consists of an entire message
not containing more than 12 bytes. The first bit of each byte will be the most significant bit (MSB). A transmitted
message begins with a SOF signal and ends with the EOF signal.
The data to be transmitted has to be in a specific format as follows:
idle,SOF,DATA, CRC, EOD, NB, IFR, EOF, IFS, idle
Definitions below:idle: Logic level low on communication bus
SOF: Start of Frame
DATA: Data Bytes
CRC: Cyclic Redundancy Check Error Detection Byte
EOD: End of DATA(only when IFR is used)
NB: Normalization Bit
IFR: In-Frame Response Byte(s)
EOF: End of Frame
IFS: Inter-Frame Separation
BRK: Break(can occur on network at any time)
Idle - Logic level low on bus any time after IFS.
Start of Frame (SOF) - The SOF signals the receiver that a new frame is beginning. SOF signal is a logic level
L5951 4/13
high pulse identified by a pulse width of about t = 200μs.
DATA - Total number of bytes that can be transmitted (from SOF to EOF) is 12 bytes.
Cyclic Redundancy Check (CRC) - A method for determining if the message received is the same as the mes-sage transmitted. If an invalid CRC number is detected, then an error will be detected. The SOF signal is not
used to determine the CRC. All bits in the CRC are initially "ones" to avoid confusion with a data stream that are
all "zeros".
End of Data (EOD) - Used to signal the receiver about the end of data transmission. If there is a IRF signal, thesender of the frame will expect one or more bytes in the IFR following the EOD. If there is no IFR used, then the
bus would stay in a logic level low state resulting in a EOF. EOD signal is recognized by a logic level low pulse
for a duration of about 200μs.
Normalization Bit (NB) - The sole reason for the NB is to define the start of the in-frame response. The first bitthe the IFR is passive, therefore it is necessary to have a signal that follows EOD. There are two forms to the
NB. First of all, the NB is a logic level high pulse. The two forms are distinguished by thier pulse widths. The first
form has a pulse width of about 64μs and indicates if the IFR contains a CRC or not. The second form has a
longer pulse width of about 128μs and also indicates if there is a CRC in the IFR or not. The manufacturer can
manipulate the NB to any of the two methods.
In-Frame Response (IFR) - Response bytes are sent by the receiver of the transmission and start after theEOD. If the IFR stays at a logic level low for a period of time then the frame must be considered to be complete.
IFR bytes can be used to send a signal back to the originator indicating the correct CRC number to confirm the
correct message was sent.
End of Frame (EOF) - Indicates the end of a frame. Once the last byte is transmitted, the bus will be in a logiclevel low state for a period of time indicating the end of the frame. EOF signal is recognized by a low pulse for
a width of about 280μs.
Inter-Frame Separation (IFS) - IFS is used to synchronize the receivers at various nodes.
ABSOLUTE MAXIMUM RATINGS* denotes active low
THERMAL DATA(*) With 6cm2 on board heat sink area.
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L5951
PIN CONNECTION
PIN FUNCTIONS*denotes active low for Sleep and Reset.
L5951 6/13
ELECTRICAL CHARACTERISTICS (Tamb = 25°C, VBAT = 14.4V unless otherwise specified. Standard Loads: IREG1 = 0.5mA, IREG2 = 0.5mA, IREG3 = 5mA)
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L5951
DC Characteristics for Class 2 TransceiverStandard Loads: IREG1 = 0.5mA, IREG2 = 0.5mA, IREG3 = 5mA
ELECTRICAL CHARACTERISTICS (continued)(Tamb = 25°C, VBAT = 14.4V unless otherwise specified. Standard Loads: IREG1 = 0.5mA, IREG2 = 0.5mA, IREG3 = 5mA)
