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L5170A
OCTAL LINE DRIVER
L5170OCTAL LINE DRIVER
ADVANCE DATAOCTAL LINE DRIVER FOR:
– EIA STD: RS232D; RS423A
– CCIT: V.10; V.28
NO EXTERNAL COMPONENTS
VERY LONG TRANSMISSION LINE (5000ft)
50V EOS OUTPUT PROTECTION
DESCRIPTIONL5170 is an octal line driver unit in DIP28 and
PLCC28 packages intended for use in the EIA std
RS232D, RS423A and CCITT V.10 and V.28 ap-
plications.
With no external components L5170 is able to
drive a line up to 5000ft assuming the line capaci-
tance is 35pF per ft and the capacitance of the fil-
ter connectors/protection components add up to
the total capacitance load. The drivers typically
run in short circuit current mode whenever the ca-
ble attached is over 500ft.
BLOCK DIAGRAM
PIN CONNECTIONS (Top views)
ABSOLUTE MAXIMUM RATINGS
Notes:
(*) Mounted on board with minimized dissipating copper area.
(**) Minimum Current per driver. Do not exceed maximum power dissipation if more than one input is on.
(***) Minimum value of the resistor used to set the slew rate.
THERMAL DATA
L5170
AC ELECTRICAL CHARACTERISTICS (VCC = 9 to 11V; VEE = – 9 to – 11V Tamb =0 to 70°C, unlessotherwise specified
Note 1: The Output under load must not drop below 90% of the open circuit drive level.
Note 2: This represents the static condition only. Applications can see 130mA normal current draw for clock and data lines with up to 500mAtransients when all lines are transitioning at the same time. Over 500ft of cable slew rate is governed by the drivers ability to sink current.
The currents are rougly equivalent to the short circuit current.
L5170
AC ELECTRICAL CHARACTERISTICS (continued)
LINE TRANSIENT IMMUNITY (Considering the following cases: Powered ON, Powered OFF-Low im-pedance power supply and Powered OFF-High impedance supply).
Note 3: The output leakage is measured under the following conditions:a) The Driver tristated
b) Power supply OFF, and the power pins shorted to Ground
c) Power supply OFF. Impedances between power pins open and power pins shorted to Ground.
Note 4: The output waveform should not show any signs of oscillations under any load variation between o.1VVss and 0.9Vss. The oscillationallowed when VSS < 0.1VSS and Vss >0.9Vss shall be 10% of Vss.
Note 5: tfc1 thru trc4 shall be within ±20% of trc1 thru trc4 respectively.
Note 6: All pins are required to withstand parameter.
Note 7: Output pins are required to withstand fig.5 without any degradation to the circuit.
TEST CIRCUIT
L5170
Figure 1: Output Leakage Test Circuit
Figure 2: Output Voltage Rise Time
Figure 3: EOS Requirements
L5170