L4992 ,TRIPLE OUTPUT POWER SUPPLY CONTROLLERELECTRICAL CHARACTERISTICS IN J OSC (V = 12V; T = 25°C; V = GND; unless otherwise specified.)Symbol ..
L4993D ,Low drop voltage regulator with watchdogFeatures Max DC supply voltage V 40VSMax output voltage toleranceV +/-2%0Max dropout volta ..
L4993DTR ,Low drop voltage regulator with watchdogAbsolute maximum ratings . . 7Table 4. Thermal data . . . . . 7Table 5. General ..
L4993DTR ,Low drop voltage regulator with watchdogBlock diagram . . . . 5Figure 2. Pins configuration . 6Figure 3. Output voltage vs. T ..
L4993MD ,Low drop voltage regulator with watchdogElectrical characteristics curves 112.5 Test circuit and waveforms plot 152.5.1 Load regul ..
L4995AK , 5V, 500mA low drop voltage regulator
LBR2012T100K , Wire-wound Chip Inductors (LB series)
LBR2012T100K , Wire-wound Chip Inductors (LB series)
LBR2012T1R0M , WOUND CHIP INDUCTORS
LBR2518T1R0M , WOUND CHIP INDUCTORS
LBS11503 , 114.99MHz SAW Filter 2MHz Bandwidth
LBSS123LT1G , N-CHANNEL POWER MOSFET
L4992
TRIPLE OUTPUT POWER SUPPLY CONTROLLER
L4992TRIPLE OUTPUT POWER SUPPLY CONTROLLER
DUAL PWM BUCK CONTROLLERS (3.3V
and 5.1V)
12V/120mA LINEAR REGULATOR
DUAL SYNCH RECTIFIERS DRIVERS
96% EFFICIENCY ACHIEVABLE
50μA (@ 12V) STAND BY CONSUMPTION
5.5V TO 25V SUPPLY VOLTAGE
EXCELLENT LOAD TRANSIENT RESPONSE
DISABLE PULSE SKIPPING FUNCTION
POWER MANAGEMENT:
- UNDER AND OVERVOLTAGE OUTPUT
DETECTION
- POWER GOOD SIGNAL
- SEPARATED DISABLE
THERMAL SHUTDOWN
PACKAGE: TQFP32
APPLICATIONNOTEBOOK AND SUBNOTEBOOK COM-
PUTERS
PEN TOP AND PORTABLE EQUIPMENT
COMMUNICATING COMPUTERS
DESCRIPTIONThe L4992 is a sophisticated dual PWM step-
down controller and power monitor intended for
Notebook computer and/or battery powered
equipment. The device produces regulated
+3.3V, +5.1V and 12V supplies for use in portable
and PCMCIA applications.
The internal architecture allows to operate with
minimum external components count. A very high
switching frequency (200/300 KHz or externally
synchronizable) optimizes their physical dimen-
sions.
Synchronous rectification and pulse skipping
mode for the buck sections optimise the overall
efficiency over a wide load current range (96% ef-
ficiency @1A/5.1V and 93% efficiency @
0.05A/5.1V.
The two high performance PWM controllers for
+3.3V and +5.1V lines are monitored for overvol-
tage, undervoltage and overcurrent conditions.
On detection of a fault, a POWER GOOD signal
is generated and a specific shutdown procedure
takes place to prevent physical damage and data
corruption.
A disable function allows to manage the output
power sections separately, optimising the quies-
cent consumption of the IC in stand-by conditions.
SYSTEM BLOCK DIAGRAM
ABSOLUTE MAXIMUM RATINGS
THERMAL DATA
BLOCK DIAGRAM
PIN CONNECTION (Top view)
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PIN FUNCTIONS
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ELECTRICAL CHARACTERISTICS (VIN = 12V; TJ = 25°C; VOSC = GND; unless otherwise specified.)(*) Guaranteed by design, not tested in production
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ELECTRICAL CHARACTERISTICS (Continued)
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DETAILED FUNCTIONAL DESCRIPTIONIn the L4992 block diagram six fundamental functional blocks can be identified:
3.3V step-down PWM switching regulator (pins 17 to 20, 24 to 27).
5.1V step-down PWM switching regulator (pins 1, 4 to 8, 30 to 32).
12V low drop-out linear regulator (pins 21,22).
5V low drop-out linear regulator (pin 3).
3.3V reference voltage generator (pin 12).
Power Management section (pins 9 to 11, 14,16).
The chip is supplied through pin VIN (2), typically by a battery pack or the output of an AC-DC adapter,
with a voltage that can range from 5.5 to 25V. The return of the bias current of the device is the signal
ground pin SGND (13), which references the internal logic circuitry.
The drivers of the external MOSFET’s have their separate current return for each section, namely the
power ground pins PGND3 (28) and PGND5 (29). Take care of keeping separate the routes of signal
ground and the two power ground pins when laying out the PCB (see "Layout and grounding" section).
The two PWM regulators share the internal oscillator, programmable or synchronizable through pin OSC
(15).
+3.3V AND +5.1V PWM REGULATORS
Each PWM regulator includes control circuitry as well as gate-drive circuits for a step-down DC-DC con-
verter in buck topology using synchronous rectification and current mode control.
The two regulators are independent and almost identical. As one can see in the Block Diagram, they
share only the oscillator and the internal supply and differ for the pre-set output voltages and for the con-
trol circuit that links the +3.3V section to the operation of the 12V linear regulator (see the relevant sec-
tion).
Each converter can be turned on and off independently: RUN3 and RUN5 are control inputs which dis-
able the relevant section when a low logic level (below 0.8 V) is applied and enable its operation with a
high logic level (above 2.4 V). When both inputs are low the device is in stand-by condition and its cur-
rent consumption is extremely reduced (less than 120μA over the entire input voltage range).
OscillatorThe oscillator, which does not require any external timing component, controls the PWM switching fre-
quency. This can be either 200 or 300 kHz, depending on the logic state of the control pin OSC, or else
can be synchronized by an external oscillator.
If OSC is grounded or connected to pin REG5 (5V) the oscillator works at 200kHz. By connecting OSC to
a 2.5 V voltage, 300 kHz operation will be selected. Instead, if pin OSC is fed with an external signal like
the one shown in fig. 1, the oscillator will be synchronized by its falling edges.
Considering the spread of the oscillator, synchronization can be guaranteed for frequencies above
230kHz. Even though a maximum frequency value is in practice imposed by efficiency considerations it
should be noticed that increasing frequency too much arises problems (noise, subharmonic oscillation,
etc.) without significant benefits in terms of external component size reduction and better dynamic per-
formance.
The oscillator imposes a time interval (300 ns min.), during which the high-side MOSFET is definitely
OFF, to recharge the bootstrap capacitor (see "MOSFET’s Drivers" section). This, implies a limit on the
maximum duty cycle (88.5% @ fsw = 300kHz, 92.6% @ fsw = 200kHz, worst case) which, in turn, im-
poses a limit on the minimum operating input voltage.
PWM regulationThe control loop does not employ a traditional error amplifier in favour of an error summing comparator
which sums the reference voltage, the feedback signal, the voltage drop across an external sense resis-
tor and a slope compensation ramp (to avoid subharmonic oscillation with duty cycles greater then 50%)
with the appropriate signs.
The output latch of both controllers is set by every pulse coming from the oscillator. That turns off the
low-side MOSFET (synchronous rectifier) and, after a short delay (typ. 75 ns) to prevent cross-conduc-
tion, turns on the high-side one, thus allowing energy to be drawn from the input source and stored in the
inductor.
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Figure 1: Synchronization signal and operation.
DETAILED FUNCTIONAL DESCRIPTION (continued)
Figure 2: L4992 Control Loop.The error summing, by comparing the above mentioned signals, determines the moment in which the
output latch is to be reset. The high-side MOSFET is then turned off and the synchronous rectifier is
turned on after the appropriate delay (typ. 75 ns), thus making the inductor current recirculate. This state
is maintained until the next oscillator pulse.
With reference to the schematic of fig. 2, the open-loop transfer function of such a kind of control system,
under the assumption of an ideal slope compensation, is:
F(s) = A⋅ RO
Rsense ⋅ 1 + s ⋅ ESR ⋅ CO
(1 + s ⋅ RO CO) ⋅ (1 + s ⋅ RF CF)
where A is the gain of the error summing comparator, which is 2 by design.
The system is inherently very fast since it tends to correct output voltage deviations nearly on a cycle-by-
cycle basis. Actually, in case of line or load changes, few switching cycles can be sufficient for the tran-
sient to expire.
The operation above illustrated is modified during particular or anomalous conditions. Leaving out other
circumstances (described in "Protections" section) for the moment, consider when the load current is low
enough or during the first switching cycles at start-up: the inductor current may become discontinuous,
that is it is zero during the last part of each cycle. In such a case, a "zero current comparator" detects the
event and turns off the synchronous rectifier, avoiding inductor current reversal and reproducing the
natural turn-off of a diode when reverse biased. Both MOSFET’s stay in off state until the next oscillator
pulse.
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Synchronous rectification.Very high efficiency is achieved at high load current with the synchronous rectification technique, which
is particularly advantageous because of the low output voltage. The low-side MOSFET, that is the syn-
chronous rectifier, is selected with a very low on-resistance, so that the paralleled Schottky diode is not
turned on, except for the small time in which neither MOSFET is conducting. The effect is a considerable
reduction of power loss during the recirculation period.
Although the Schottky might appear to be redundant, it is not in a system where a very high efficiency is
required. In fact, its lower threshold prevents the lossy body-diode of the synchronous rectifier MOSFET
from turning on during the above mentioned dead-time. Both conduction and reverse recovery losses are
cut down and efficiency can improve of 1-2% in some cases. Besides a small diode is sufficient since it
conducts for a very short time.
As for the 3.3V section only, the synchronous rectifier is also involved in the 12 V linear regulator opera-
tion (see the relevant section). See also the "Power Management" to see how both synchronous rectifi-
ers are used to ensure zero voltage output in stand-by conditions or in case of overvoltage.
Pulse-skipping operation.To achieve high efficiency at light load current as well, under this condition the regulators change their
operation (unless this feature is disabled): they abandon PWM and enter the so-called pulse-skipping
mode, in which a single switching cycle takes place every many oscillator periods.
The "light load condition" is detected when the voltage across the external sense resistor (VRsense) does
not exceed 26mV while the high-side MOSFET is conducting. When the reset signal of the output latch
comes from the error summing comparator while VRsense is below this value, it is ignored and the actual
reset is driven as soon as VRsense reaches 26mV. This gives some extra energy that maintains the output
voltage above its nominal value for a while. The oscillator pulses now set the output latch only when the
feedback signal indicates that the output voltage has fallen below its nominal value. In this way, most of
oscillator pulses is skipped and the resulting switching frequency is much lower, as expressed by the fol-
lowing relationship:
fps = K ⋅ Rsense2 ⋅ Iout ⋅ Vout ⋅
1 − Vout
Vin
where K = 3.2 ⋅ 103 and fps is in Hz. As a result,
the losses due to switching and to gate-drive,
which mostly account for power dissipation at low
output power, are considerably reduced.
The +5.1V section can work with the input voltage
very close to the output one, where the current
waveform may be so flat to prevent pulse-skipping
from being activated. To avoid this, the pulse-skip-
ping threshold (of the +5.1V section only) is
roughly halved at low input voltages, as shown in
fig. 3. Under this condition, in the above formula
the constant K becomes 12.8 ⋅ 103.
When in pulse-skipping, the output voltage is
some ten mV higher than in PWM mode, just be-
cause of its mode of operation. If this "load regula-
tion" effect is undesirable for any reason, the pulse
skipping feature can be disabled (see "Power
Management" section) to the detriment of effi-
ciency at light load.
MOSFET’s driversTo get the gate-drive voltage for the high-side N-channel MOSFET a bootstrap technique is employed. A
capacitor is alternately charged through a diode from the 5V REG5 line when the high-side MOSFET is
OFF and then connected to its gate-source leads by the internal floating driver to turn the MOSFET on.
The REG5 line is used to drive the synchronous rectifier as well, and therefore the use of low-threshold
Figure 3: Pulse-skipping threshold vs. inputvoltage (+5.1V section only).
DETAILED FUNCTIONAL DESCRIPTION (continued)
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MOSFET’s (the so-called "logic-level" devices) is highly recommended.
The drivers are of "dynamic" type, which means they do not give origin to current consumption when
they are in static conditions (ON or OFF), but only during transitions. This feature is aimed at minimizing
the power consumption of the device even during stand-by when both low-side MOSFET’s are ON.
ProtectionsEach converter is fully protected against fault conditions. A monitoring system checks for overvoltages of
the output, quickly disabling both converters in case such an event occurs. This condition is latched and
to allow the device to start again either the supply voltage has to be removed or both RUN3 and RUN5
pins have to be driven low.
Undervoltage conditions are detected as well but do not cause interruption of the operation of the convert-
ers. Only PWROK signal (at pin 10) reveals the anomaly with a low output level.
If the chip overheats (above 135 °C typ.) the device stops operating as long as the temperature falls below a
safe value (105 °C typ.). The overtemperature condition is signalled by a low level on PWROK as well.
A current limitation comparator prevents from excessive current in case of overload or short-circuit. It in-
tervenes as the voltage VRsense exceeds 100 mV, turning off the high-side switch before the error sum-
ming does. By the way, this also gives the designer the ability to program the maximum operating current
by selecting an appropriate sense resistor.
This pulse-by-pulse limitation gives a quasi-constant current characteristic. If a "folded back" charac-
teristic, like the one shown in Fig. 4a, is desired the external circuit of Fig. 4b can be used. The circuits
acts on the current limitation and is extremely simple and cheap. The advantage of such a technique i
that a short circuit will cause a current much lower than the maximum to flow. Th e stress of the power
components will be very little and no overheating will occur. The part values shown in Fig. 4b produce
IFOLD = 1A in the Demo Board (see the relevant section).
Inrush current at start-up is reduced with soft-start. An external capacitor (one for each converter) is
charged by an internal 4μA current generator and its linearly ramping voltage increases the setpoint of
the current limit comparator, starting from zero up to the final value of 100 mV. Thus duty cycle reaches
gradually its steady-state value and dangerous current peaks as well as overshoots of the output voltage
are avoided.
+12 V LINEAR REGULATOR
The +12V Linear regulator is capable of delivering up to 120 mA to an external load through pin REG12.
It is supplied from pin V13IN which accepts voltages included in the range of 13 to 20V.
If the application works with input voltages included between 14 and 20V, the supply for the regulator
can be obtained directly from the input source. If such is not the case, the most convenient way to get
the supply is to use an auxiliary winding on the 3.3 V section inductor with a catch diode, Ds, and a filter
capacitor, Cs, as shown in fig. 5. This winding delivers energy to pin V13IN during the recirculation pe-
riod of each switching cycle with a voltage determined by the turns ratio n and little dependent on the in-
put voltage.
DETAILED FUNCTIONAL DESCRIPTION (continued)
Figure 4.
L49929/26
An auxiliary winding could be used also on the choke of the +5.1V section, either to power the +12V lin-
ear regulator or to derive a further supplemental output, however the 3.3 V section has been provided
with some features aimed at ensuring a proper operation under all circumstances.
For a correct operation of the regulator, the voltage at pin V13IN must not be too low. The flyback con-
nection of the two windings ensures a well regulated voltage, provided there is good magnetic coupling.
The coupled inductors configuration, however, is not able to sustain the auxiliary voltage if the main out-
put is lightly loaded: the secondary voltage drops and the system goes out of regulation.
To overcome this problem, when the V13IN voltage falls below a certain threshold (13.7 V +/- 5%) be-
cause of too light a load on the 3.3V section, the relevant synchronous rectifier is turned on for 1.5 μs
max. during the interval in which the inductor current is zero ("one-shot" feature, see fig. 6). In this way,
the inductor current reverses and draws from the output capacitor energy which is forward transferred to
the auxiliary output.
In case the 3.3V section is working at full load and the linear regulator is lightly loaded, the voltage at pin
V13IN can exceed the expected value. In fact, Ds and Cs act as a peak-holding circuit and V13IN is in-
fluenced by the voltage spikes at switching transients. An internal clamp limits the voltage but, in case of
intervention, the chip power dissipation will rise.
When the 3.3V regulator is disabled, the linear regulator is disabled as well and is placed in a low-power
mode to reduce device consumption.
DETAILED FUNCTIONAL DESCRIPTION (continued)
Figure 5: 12V regulator supply with auxiliary winding.
Figure 6: "One shot" feature to sustain V13IN voltage.
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+5 V LINEAR REGULATOR & +3.3 V REFERENCE VOLTAGE GENERATOR
This low drop-out regulator powers almost all the internal circuitry, that is the +3.3V reference voltage
generator, amplifiers, comparators, digital logic, and MOSFET drivers. Its output is externally available
through pin REG5.
The typical external use of this generator is to charge the bootstrap capacitors used to produce the gate-
drive voltage for the high-side MOSFET’s of both PWM converters.
At start-up and when the 5V section is not operating, this regulator is powered by the chip input voltage.
To reduce power consumption, the linear regulator is turned off and the REG5 pin is internally connected
to the 5V PWM regulator output via V5SW pin, when the 5V PWM regulator is active and its output volt-
age is above the switchover threshold, 4.5V.
The 5V regulator is always active, even if both PWM regulators are disabled, as long as power is applied
to the chip.
The 3.3V reference voltage generator, which is active only when either PWM converter is enabled, pro-
vides comparison levels for threshold detection and device operation. It is allowed to source up to 5mA
to an external load from its buffered output, externally available through pin VREF.
If either REG5 or VREF does not deliver the correct voltage, the device is shut down.
POWER MANAGEMENT
The L4992 is provided with some control pins suitable to perform some functions which are commonly
used or sometimes required in battery-operated equipment. Besides, it features controlled timing se-
quences in case of turn-on/off and device shutdown for a safe and reliable behaviour under all condi-
tions.
As above mentioned, RUN3 and RUN5 pins allow to disable separately both PWM converters by means
of logic signals (likely coming from a μP) as mentioned earlier.
NOSKIP can disable the pulse-skipping feature: when it is held high neither of the PWM regulators is al-
lowed to enter this kind of operation.
The PWROK output signal drives low immediately when either PWM regulator output falls below its own
undervoltage threshold or when either of them is disabled. It is high when both regulator run properly.
A capacitor connected between CRST and ground fixes a time, in the order of 2ms/nF, which delays the
transition low-high of PWROK. This happens at start-up or after recovering an undervoltage condition,
provided both RUN3 and RUN5 are high. The delay starts from the moment in which the output voltage
has reached its correct value for both sections.
The same delay intervenes also in another circumstance: when a section is disabled (because its RUN is
driven low or owing to a thermal shutdown), the relevant synchronous rectifier is turned on after the
above delay in order to make sure that the load is no longer supplied.
This delay, however, does not intervene in case of overvoltage: the synchronous rectifier is immediately
turned on after the shutdown, thus acting as a built-in "crowbar".
All these timing sequences are illustrated in Fig 7.
DETAILED FUNCTIONAL DESCRIPTION (continued)
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DETAILED FUNCTIONAL DESCRIPTION (continued)
Figure 7: L4992 controlled timing sequences.
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Basically, the application circuit topology is fixed, and the design procedure concerns only the selection
of the component values suitable for the voltage and current requirements of the specific application.
The design data one needs to know are therefore:
Input voltage range: the minimum (Vinmin) and the maximum (Vinmax) voltage under which the applica-
tion is expected to operate;
Maximum load current for each of the three sections:
- Iout3 for the +3.3V section;
- Iout5 for the +5.1V section:
- Iout12 for the +12V section;
Maximum peak-to-peak ripple amplitude of the output voltage for each switching section:
- Vrpp3 for the +3.3V section;
- Vrpp5 for the +5.1V section;
The operating frequency fsw (200/300 kHz or externally synchronized).
It is worth doing some preliminary considerations. The selection of the switching frequency depends on
the requirements of the application. If the aim is to minimize the size of the external components, 300
kHz will be chosen. For low input voltage applications 200 kHz is preferred, since it leads to a higher
maximum duty cycle.
As for the switching regulators, the inductance value of the output filter affects the inductor current ripple:
the higher the inductance the lower the ripple. This implies a lower current sense resistor value (for a
given Iout), lower core losses and a lower output voltage ripple (for a given output capacitor) but, on the
other hand, more copper losses and a worse transient behaviour due to load changes. Usually the maxi-
mum ripple peak-to-peak amplitude (which occurs at Vinmax) is chosen between 15% and 50% of the full
load current. It is convenient to introduce a ripple factor coefficient, RF, that is therefore a number be-
tween 0.15 and 0.5.
As for the linear regulator, its input voltage Vinlin should not fall below 13V and therefore the auxiliary
winding should be dimensioned to get this voltage with a certain margin (say, 14V). Conversely, an
higher input voltage leads to higher losses inside the regulator, to the detriment of efficiency, and to
higher total current on the +3.3V inductor. Besides it implies a higher turns ratio and therefore a worse
magnetic coupling, which affect energy transfer during flyback.
SWITCHING REGULATORS
+5.1V InductorTo define the inductor, it is necessary to determine firstly the inductance value. Its minimum value is
given by:
L5min = 5.1 ⋅ (Vin max − 5.1)
Vin max ⋅ fsw ⋅ Iout5 ⋅ RF
and a value L5 > L5min should be selected.
Core geometry selection is connected to the requirements of the specific application in terms of space
utilization and other practical issues like ease of mounting, availability and so on. As to the material, the
choice should be directed towards ferrite, molypermalloy or Kool Mμ® , to achieve high efficiency. These
materials provide low core losses (ferrite in particular), so that the design can be concentrated on pre-
venting saturation and limiting copper losses.
Saturation must be avoided even at maximum peak current:
IL5pk = Iout5 + 5.1 ⋅ (Vin max − 5.1)
2 ⋅ fsw ⋅ L5 ⋅ Vin max
To limit copper losses, the winding DC resistance, RL, should be as low as possible (in the range of mΩ).
AC losses can usually be neglected. A practical criterion to minimize DC resistance could be to use the
largest wire that fits the selected core.
Anyway the best solution, whenever possible, is to use an off-the-shelf inductor which meets the require-
ments in terms of inductance and maximum DC current. Nowadays there is a broad range of products
DESIGN PROCEDURE
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