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L4990-L4990A-L4990AD-L4990D
PRIMARY CONTROLLER
L4990
L4990APRIMARY CONTROLLER
CURRENT-MODE CONTROL PWM
SWITCHING FREQUENCY UP TO 1MHz
LOW START-UP CURRENT< 0.45mA
HIGH-CURRENT OUTPUT DRIVE SUITABLE
FOR POWER MOSFET (1A)
FULLY LATCHED PWM LOGIC WITH DOU-
BLE PULSE SUPPRESSION
PROGRAMMABLE DUTY CYCLE
100% AND 50% MAXIMUM DUTY CYCLE
LIMIT
PROGRAMMABLE SOFT START
PRIMARY OVERCURRENT FAULT DETEC-
TION WITH RE-START DELAY
PWM UVLO WITH HYSTERESIS
IN/OUT SYNCHRONIZATION
DISABLE LATCHED
INTERNAL 100ns LEADING EDGE BLANK-
ING OF CURRENT SENSE
PACKAGE: DIP16 AND SO16W
DESCRIPTIONThis primary controller I.C., developedin BCD60II
technology, has been designedto implement off
lineor DC-DC power supply applications usinga
fixed frequency current mode control.
Basedona standard current mode PWM control-
ler this device includes some features as pro-
grammable soft start, IN/OUT synchronization,
disable (to be used for over voltage protection
and for power management), precise maximum
Duty Cycle Control, 100ns (typ) leading edge
blankingon current sense, pulseby pulse current
limit and overcurrent protection with soft start in-
tervention.
July 1999
TIMING214
Vref
CLK
2.5V1.2V
BLANKING
PWM
FAULT
SOFT-START
25V
16V/10V
VREFOK
DIS
E/A R
DIS
2.5V8151
13V
PWMUVLO
SGND COMP
ISEN
DIS
RCT
SYNC DC-LIM VCC VREF
D98IN1002
VFB
PGND
OUT
OVER CURRENT
BLOCK DIAGRAM
ORDERING NUMBERS: L4990/L4990A(DIP16)
L4990D/L4990AD (SO16W)
MULTIPOWER BCD TECHNOLOGY
DIP16 SO16W1/24
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value UnitVCC Supply Voltage(ICC< 50mA)(*) selflimit V
IOUT Output Peak Pulse Current 1.5 A
Analog Inputs& Outputs (6,7) -0.3to8 V
Analog Inputs& Outputs (1,2,3,4,5,15,1413) -0.3to6 V
Ptot Power Dissipation@ Tamb =70°C1 W Junction Temperature, Operating Range -25to 125 °C
Tstg Storage Temperature, Operating Range -55to 150 °C
(*) maximum package power dissipationlimits must beobserved
THERMAL DATA
Symbol Parameter Value UnitRthj-amb Thermal Resistance Junctionto Ambient
DIP16 80 °C/W
Rthj-amb Thermal Resistance Junctionto Ambient
SO16 120 °C/W
PIN FUNCTIONS Name Function SYNC Synchronization.A synchronization pulse terminates the PWM cycle and dischargesCt RCT Oscillatorpinfor external Ct,Rt components DC Duty Cycle control VREF 5.0V +/-1.5% reference voltage VFB Error Amplifier Inverting input COMP Error Amplifier Output SS Soft startpinfor external capacitor Css
8VCC Supplyfor internal ”Signal” circuitry
9VC Supplyfor Power section OUT High current totem pole output PGND Power ground SGND Signal ground ISEN Current sense DIS Disable.It must neverbe leftfloating. Tieto SGNDif notused. DC-LIM Connecting this pinto Vref, DCis limitedto 50%.Ifitisleft floatingor groundedno limitationis
imposed NC Not connected
SYNC
RCT
VREF
VFB
COMP OUT
SGND
PGND
ISEN
DIS
DC-LIM
N.C.16
D95IN197CC 8VC9
PIN CONNECTION
L4990- L4990A2/24
ELECTRICAL CHARACTERISTICS (VCC= 15V;Tj=0to 70°C; unless otherwise specified.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
REFERENCE SECTION Output Voltage Tj =25°C;IO= 1mA 4.925 5.0 5.075 V
Line Regulation VCC=12to 20V 2.0 15 mV
Load Regulation IO=1to 20mA 5.0 20 mV Temperature Stability 0.4 mV/°C
Total Variation Line, Load, Temperature 4.875 5.0 5.125 V
IOS Short Circuit Current Vref=0V 30 150 mA
Power Down/UVLO VCC= 8.5V; Isink= 0.5mA 0.2 0.5 V
OSCILLATOR SECTIONInitial Accuracy Tj =25°C;RT= 4.42kΩ;
CT= 1nF;pin15 Vref
285 300 315 kHz
Accuracy RT= 4.42KΩ;VCC=12to 20V;
CT= 1nF;pin15= Vref
279 300 321 kHz
Initial Accuracy Tj =25°C;RT= 4.42KΩ;
CT= 1nF;pin15 OPEN
280 295 310 kHz
Accuracy RT= 4.42KΩ;VCC=12to 20V;
CT= 1nF;pin15 OPEN
275 295 315 kHz
Duty Cycle pin3= 0,7V,pin15= Vref
pin3= 0.7V,pin15= OPEN
Duty Cycle RT= 4.42kΩ CT= 1nF
pin3= 3.2V,pin15= Vref
pin3= 3.2V,pin15= OPEN
Duty Cycle Accuracy pin3= 2.02V,pin15= OPEN 37 40 43 %
Oscillator Ramp Peak 3.0 V
Oscillator Ramp Valley 1.0 V
ERROR AMPLIFIER SECTIONInput Bias Current VFBto GND 0.2 1.0 μA Input Voltage VCOMP =VFB 2.42 2.5 2.58 V
GOPL Open Loop Gain VCOMP= 2to4V 60 90 dB
SVR Supply Voltage Rejection VCC=12to 20V 85 dB
VOL Output Low Voltage Isink= 2mA, VFB= 2.7V 1.1 V
VOH Output High Voltage Isource= 0.5mA, VFB= 2.3V 5 6 V Output SourceCurrent VCOMP> 4V,VFB= 2.3V 0.5 1.3 mA
Output Sink Current VCOMP= 1.1V, VFB= 2.7V 2 6 mA
Unit Gain Bandwidth 2 4 MHz Slew Rate 8 V/μs
PWM CURRENT SENSE SECTION Input Bias Current Isen =0 3 15 μA Maximum Input Signal VCOMP=5V 0.92 1.0 1.08 V
Delayto Output 100 ns
Gain 2.85 3 3.15 V/V
SOFT STARTISSC SS Charge Current 14 20 26 μA
ISSD SS Discharge Current VSS= 0.6V 200 μA
VSSSAT SS Saturation Voltage DC= 0% 0.6 V
VSSCLAMP SS Clamp Voltage 7 V
LEADING EDGE BLANKINGInternal Masking Time 100 ns
L4990- L4990A3/24
FUNCTIONAL DESCRIPTIONThe I.C. containsa standard PWM current mode
control section with improved performance with
respectto the UC384X family.
Enhanced features include start-up bias current
reducedto< 270μA (typ), improved E/A perform-
ance (4MHz B/W, 1.3mA Source Current, high-
slew rate) accurate 1MHz oscillator, and also re-
duced propagation delaysin the critical path from
Current Senseto Output.
ADDITIONAL FEATURES
Soft Start (SS) external capacitoris charged by an internal
constant current source (20μA)to generatea SS
signal which clamps the E/A output
The SS pin doublesasa Fault Reset Delay func-
tionas described below.
Current Limit/ Reset Delay internal high-speed current limit comparator
ELECTRICAL CHARACTERISTICS (continued.)
Symbol Parameter Test Condition Min. Typ. Max. Unit
OUTPUT SECTIONVOL Output Low Voltage IO= 250mA 1.0 V
VOH Output High Voltage IO= 20mA; VCC= 12V 10 10.5 V= 200mA; VCC= 12V 9 10 V
VOUT CLAMP Output Clamp Voltage IO= 5mA; VCC= 20V 13 V
Collector Leakage VCC= 20V VC= 24V 100 200 μA
Fall Time CO= 1nF= 2.5nF ns
Rise Time CO= 1nF= 2.5nF
100 ns
UVLO Saturation VCC =0Vto VCCON;Isink= 10mA 1.0 V
SUPPLY SECTIONVCCON Startup voltage
L4990
L4990AVCCOFF Minimum Operating Voltage
L4990
L4990AVhys Voltage After Turn-on Hysteresis
L4990
L4990A0.8 StartUp Current Before Turn-onat:
VCC =VCCON- 0.5V
100 270 450 μA
Iop Operating Current CT =1nF,RT= 4.42kΩ,CO =1nF 12 18 mA Quiescent Current (After turn on),Co =0nF= 1nF,RT= 4.42kΩ,
7.0 10 mA
ISH Shutdown Current 100 270 450 μA Zener Voltage I8= 20mA 21 25 30 V
SYNCHRONIZATION SECTION
Master Operation Clock Amplitude ISOURCE= 0.8mA 4 V Clock Source Current Vclock= 3.5V 7 mA
Slave Operation Sync Pulse Low Level 1 V
High Level 3.5 V Sync Pulse Current VSYNC= 3.5V 0.8 mA
OVER CURRENT PROTECTION Fault Threshold Voltage 1.1 1.2 1.3 V
DISABLE SECTIONShutdown threshold 2.4 2.5 2.6 V
L4990- L4990A4/24
referencedto 1.2V detects primary over-current
conditions. On detectionof an overcurrent fault
the outputis immediately shutdown and the fault also latched.A Fault Reset Delayis imple-
mented by discharging the external Soft Start
(SS) timing capacitor before resetting the fault
latch and initiatinga softstart cycle. caseofa continuous fault condition the SS ca-
pacitoris chargedto 5V before being discharged
again,to ensure that the fault frequency does not
exceed the programmedsoft start frequency.
Duty Cycle Limit simple connection between the DC-LIM and the
available Vref activatesan internalT- FlipFlop lim-
iting the DCto about 50%.If this pinis not con-
nectedor grounded, the limitof the duty cycleis
extendedto about 100%
Duty Cycle ControlDuty Cycle DCis externally programmedby set-
tinga voltage between 1V (0% DC) and 3V
(100% DC)at the DC pin. The programmed volt-
ageis compared with the oscillator CT capacitor
charging waveformto determine the maximum
ON-timein each period. This function givesa fine
controlof DC. this pinis floating the maximum duty cycle de-
pendson DC-LIM status.
Synchronization SYNC pin eases Synchronizationof theICto
the external world( e.g. anotherIC workingin
parallelorto TV/monitorsync signal). TV/monitor applications the timing components
RT,CT are set fora frequency lower than the
minimum TV sync frequency. When the TV circuit
has powered-upit takes over and the system fre-
quencyis thatof the SYNC. Duty Cycleis control-
lable using the DC function. parallel operationof several IC’s no Mas-
ter/Slave designationis requiredas the higherfre-
quencyICis automatically the master. Controllers be synchronized have their SYNC pins tied to-
gether and each SYNC pin operatesasa bidirec-
tional circuit. The firstICto driveits SYNC pinis
the master andit initiatesa dischargeof the CT
timing capacitorof every controller. The Sync in-
put signalis edge-triggered and sets an internal
”sync latch” which ensures full dischargeof CT.
Disable FunctionThe DIS pin performsa logic level latched-shut-
down function. When pulled above 2.5Vit shuts
down the completeIC witha standby currentof
<270μA (typ). reset theIC the VCC pin mustbe pulled-down
below the lower UVLO threshold (10V).
Leading Edge Blanking (LEB) LEB intervalof 100ns has been incorporated
into theICto blank out the current sense signal
during the first 100ns from switch turn-on.
This provides noise immunityto turn-on spikes
and reduces external RC filtering requirementson
the current-sense signal.
V14=0, OSC=disabled= 25°C 4 8 1216 2024
Vcc[V] [mA]
Y
Figure1. Quiescent current vs. input voltage.= 7.6V andY= 8.4V for L4990A) 1012 141618 202224
Vcc [V] [uA]
V14= Vref= 25°C
Figure2. Quiescent current vs. input voltage
(after disable).
L4990- L4990A5/24
1012 1416182022 24Vcc [V][mA]
V14=0,V5= Vref= 4.5Kohm,Tj= 25°C
500Khz
300Khz
1Mhz
100Khz
Figure3. Quiescent current vs. input voltage.-50 -25 0 25 50 75 100 125 150
5.1 (°C)
Vref [V])
Vcc= 15V
Iref= 1mA
Figure7. Vref vs. junction temperature.-50 -25 0 25 50 75 100 125 150
5.1 (°C)
Vref[V]
Vcc= 15V
Iref= 20mA
Figure8. Vref vs. junction temperature. 101214161820220
Vcc[V] [mA]= 1nF,Tj= 25°C= 100%
1MHz
500KHz
300KHz
100KHz
Figure
5. Quiescent current vs. input voltage
and switching frequency. 5 10 15 20 25
Iref [mA]
Vref[V]
Vcc=15V= 25°C
Figure6. Reference voltage vs. load current. 10121416 18 20 22
Vcc[V] [mA]= 1nF,Tj= 25°C=0%
1MHz
500KHz
300KHz
100KHz
Figure
4. Quiescent current vs. input voltage
and switchingfrequency.
L4990- L4990A6/24
-50 -25 0 25 50 75 100 125 150
320 (°C)
fsw (KHz)
Rt= 4.5Kohm,Ct= 1nF
Vcc= 15V, V15=Vref
Figure 14.Switchingfrequency vs.temperature. 0.2 0.4 0.6 0.8 1 1.26
Isource[A]
Vsat=V [V]
Vcc= 15V= 25°C
Figure 10. Output saturation. 0.2 0.4 0.6 0.8 1 1.20
Isink[A]Vsat=V [V]
Vcc= 15V= 25°C
Figure 11. Output saturation. 10 100 1000 10000
fsw (Hz)
SVRR (dB)
Vcc=15V
Vp-p=1V
Figure9. Vref SVRR vs. switchingfrequency. 20 30 4010000
5000 (kohm)
fsw(KHz)
100pF
220pF
470pF
1nF2.2nF5.6nF
Tj= 25°C
Vcc =15V ,V15=0V
Figure13.Timingresistorvs.switchingfrequency. 200 400 600 800 1,000 1,200 1,4000
Vpin10 [mV]
Ipin10 [mA]
Vcc
beforeturn-on
Figure 12. UVLO Saturation
L4990- L4990A
7/24
0.01 0.1 1 10 100 1000 10000 100000
f(KHz) [dB] Phase
Figure 19. E/A frequency response. 1020 3040 5060 7080 90 100
Duty Cycle [%] Control Voltage Vpin3[V]= 4.5Kohm,= 1nF
V15=0VV15= Vref
Figure 17. Maximum Duty Cyclevs Vpin3.
-50 -25 0 25 50 75 100 125 15060
Tj(°C)
Delaytooutput(ns)
PIN10=OPEN
1Vpulse
onPIN13
Figure18.Delaytooutputvsjunctiontemperature.
-50 -25 0 25 50 75 100 125 150
320 (°C)
fsw (KHz)
Rt= 4.5Kohm,Ct= 1nF
Vcc= 15V,V15=0
Figure 15. Switching frequency vs. temperature.
2468 10
1,200
1,500
TimingcapacitorCt [nF]
Dead time[ns]
Rt=4.5Kohm
V15=0V
V15=Vref
Figure 16. Dead timevs Ct.
L4990- L4990A
8/24
APPLICATION INFORMATION
Detailed Pin Functions Description
Pin1. SYNC (In/Out Synchronization). This func-
tion allows the IC’s oscillator eitherto synchronize
other controllers(master)ortobe synchronizedto externalfrequency(slave).a master, the pin delivers positive pulses dur-
ing the ramp-downof the oscillator (see pin2).In
slave operationthe circuitis edge triggered. Refer fig. 21to see howit works. When severalIC
workin parallel no master-slave designationis
needed because the fastest one becomes auto-
matically the master.
During the ramp-upof the oscillator the pinis
pulled low bya 600μA generator. During the
ramp-down, thatis when the pulseis released,
the 600μA pull-downis disconnected. The pin be-
comesa generator whose source capabilityis
typically 7mA (witha voltage still higher than
3.5V). fig. 20, some practical examplesof synchroniz-
ing the L4990 are given.
L4990 L4990
VREF
SYNCSYNC
RCTRCT
L4981A
(MASTER)
L4990
(SLAVE)
VREFSYNC
RCT
ROSC COSC CT
L4990
(MASTER)
L4981A
(SLAVE)
SYNC
ROSCCT COSC
SYNC
(a) (b) (c)
D97IN494A
VREF17 RCT 121718
Figure 20. Synchronizing the L4990.
Pin2. RCT (Oscillator).A resistor (RT) anda ca-
pacitor (CT), connectedas shownin fig.21 set the
operating frequency foscof the oscillator.is charged through RT untilits voltage reaches
3V, thenis quickly internally discharged. As the
voltage has droppedto 1Vit starts being charged
againR3
CLAMP
50ΩQ
600μA
D97IN500B
VREF
RCT
SYNC
CLK2
Figure 21. Oscillatorand synchronization internal schematic.
L4990- L4990A
9/24
The frequency can be established with the aidof
fig. 13 diagramsor considering the approximate
relationship:
fosc≅ 1⋅ (0.693⋅ RT+ KT) (1)
whereKTis defined as:=
90, V15= VREF
160 V15= GND/OPEN (2)
andis linkedto the durationof the falling edgeof
the sawtooth:≅ 30⋅10-9 +KT⋅ CT (3)is also the durationof the sync pulses deliv-
eredat pin1 and defines the upper extremeof
the duty cycle range,Dx (see pin 15 forDx defini-
tion and calculation). case V15is connectedto VREF, however, the
switching frequencyof the system will be as
highas half fosc. theICistobe synchronizedtoan externaloscil-
lator, RT and CT should be selected fora fosc
lower than the master frequencyin any condition
(typically, 10-20%), dependingon the toleranceRT andCT itself.
Pin3. DC (Duty Cycle Control). By biasing this
pin witha voltage between1 and3Vitis possible set the maximum duty cycle between0 and the
upper extremeDx (see pin 15). Dmaxis the desired maximum duty cycle, the
voltageV3tobe appliedto pin3is: =5-2 (2-Dmax) (4)
Dmaxis determined by internal comparison be-
tween V3 and the oscillator ramp (see fig. 22),
thusin case the deviceis synchronizedtoan ex-
ternal frequency fext (and therefore the oscillator
amplitudeis reduced),(4) changes into:=5−4⋅ exp Dmax⋅CT⋅ fext
(5) voltage below 1V will inhibit the driver output
stage. This couldbe used fora not-latcheddevice
disable, for examplein caseof overvoltage pro-
tection (see application ideas). no limitation on the maximum duty cycleis re-
quired (i.e. DMAX =DX), the pin hastobe left float-
ing. An internal pull-up holds the voltage above
3V. Should the pin pickup noise (e.g. during ESD
tests),it can be connectedto VREF througha
4.7kΩ resistor.
Pin4. VREF (Reference Voltage). An internal
generatorfurnishesan accuratevoltage reference
(5V±1.5%) that canbe usedto supplyan external
circuit (consider some ten mA). small film capacitor(1 μF typ.), connected be-
tween this pin and SGND,is recommendedto
preventswitching noisefromaffectingthereference.
Beforedevice turn-on, this pin hasa sink current ca-
pabilityof 0.5mA.
Pin5. VFB (Error Amplifier Inverting Input). The
feedback signalis appliedto this pin andis com-
paredto the E/A internal reference (2.5V). The
E/A output generates the control voltage which
fixes the duty cycle.
The E/A features high gain-bandwidth product,
which allowsto broaden the bandwidthof the
overall control loop, high slew-rate and current
capability, which improvesits large signal behav-
ior. Usually the compensation network, which sta-
bilizes the overall control loop,is connected be-
tween this pin and COMP (pin6).
Pin6. COMP (Error Amplifier Output). Usually,
this pinis used for frequency compensation and
the relevant networkis connected between this
pin and VFB (pin 5). Compensation networks to-
wards ground are not possible since the L4990
E/Aisa voltage mode amplifier (low output im-
pedance). See application ideas for some exam-
pleof compensationtechniques.
Pin7. SS (Soft-Start).At device start-up,a ca-
pacitor (Css) connected between this pin and
SGND (pin 12)is chargedby an internal current
generator, ISSC, up to about 7V. During this
ramp, the E/A outputis clamped by the voltage
across Css itself and allowedto rise linearly, start-
ing from zero, upto the steady-state value im-
posedby the control loop. The maximum time in-
terval during which the E/Ais clamped,referredto soft-start time,is approximately:
D97IN501A
VREF
RCT PWM LOGIC
Figure 22. Duty cycle control.
L4990- L4990A
10/24
Tss≅3⋅ Rsense⋅ IQpk
ISSC ⋅ Css (6)
where Rsenseis the current sense resistor (see pin
13) and IQpkis the switch peak current (flowing
through Rsense), which depends on the output
load. Usually, CSSis selectedfora TSSin the or-
derof milliseconds. mentioned before, the soft-start intervenes
alsoin caseof severe overloador short circuit on
the output. Referringto fig. 23, pulse-by-pulse
current limitationis somehow effectiveas longas
the ON-timeof the power switch can be reduced
(fromAto B). After the minimum ON-timeis
reached (fromB onwards) the currentis outof
control. prevent this risk,a comparator trips an over-
current handling procedure, named ’hiccup’ mode
operation, whena voltage above 1.2V (pointC)is
detected on current sense input (ISEN, pin 13).
Basically, theICis turnedoff and then soft-started longas the fault conditionis detected.Asa re-
sult, the operating pointis moved abruptlyto D,
creatinga foldback effect. Fig. 24 illustrates the
operation.
The oscillation frequency appearing on the soft-
start capacitorin caseof permanent fault, referredas ’hiccup” period,is approximatelygiven by:
Thic≅ 4.5⋅
ISSC+ 1
ISSD Css (7)
Since the system tries restarting each hiccup cy-
cle, thereis not any latchoff risk.
VOUT
TON
D.C.M. C.C.M. C
IQpk
TON(min)
1-2·IQpk
IQpk(max)
IOUTISHORT IOUT(max)D97IN495
Figure 23. Regulation characteristicand re-
lated quantities
Thic time
SHORTIOUT
ISEN
FAULT5V
0.5V
D97IN496
Figure 24. Hiccup mode operation.
L4990- L4990A
11/24
”Hiccup” keeps the systemin controlin caseof
short circuits but does not eliminate power com-
ponents overstress during pulse-by-pulse limita-
tion (fromAto C). Other external protection cir-
cuits are neededifa better controlof overloadsis
required.
Pin8. VCC (Controller Supply). This pin supplies
the signal partof the IC. The deviceis enabledas
VCC voltage exceeds the start threshold and
works as longas the voltageis above the UVLO
threshold. Otherwise the deviceis shut down and
the current consumptionis extremely low. internal Zener limits the voltage on VCCto
25V. Below this value theIC current consumption low but increases considerablyif this limitis ex-
ceeded. small film capacitor between this pin and SGND
(pin 12), placedas closeas possibleto the IC,is
recommendedto filter high frequency noise.
Pin9. VC (Supplyof the Power Stage).It sup-
plies the driverof the external switch and there-
fore absorbsa pulsed current. Thusitis recom-
mended to placea buffer capacitor (towards
PGND, pin 11, as close as possibleto the IC)
ableto sustain these current pulses andin order avoid them inducing disturbances.
This pin canbe connectedto the buffer capacitor
directlyor througha resistor,as shownin fig. 25, control separately the turn-on and turn-off
speedof the external switch, typicallya Power-
MOS.At turn-on the gate resistanceis Rg +Rg’
and turn-offisRg only.
Pin 10. OUT (Driver Output). This pinis the out-
put of the driver stageof the external power
switch. Usually, this will bea PowerMOS, al-
though the driveris powerful enoughto drive
BJT’s (1.6A source, 2A sink, peak).
The driveris madeupofa totem pole witha high-
side NPN Darlington anda low-side VDMOS, and
deliversa voltage internally clamped,as shownin
fig. 25. Thusitis possibleto supply the driver (pin with higher voltages without any problemof
damage for the gate oxideof the external MOS,
but,of course, the power dissipationon theIC will
increase. UVLO conditions an internal circuit (shownin
fig.26) holds the pin lowin orderto ensure that
the external MOS cannot be turned on acciden-
tally. The peculiarityof this circuitisits abilityto
mantain the same sink capability (typically, 20mA 1V) from VCC= 0Vupto the start-up threshold.
When the thresholdis exceeded and the L4990
starts operating, VREFOKis pulled high (referto
fig. 26) and the circuitis disabled.is then possibleto omit the ”bleeder” resistor
(connected between the gate and the sourceof
the MOS) ordinarily usedto prevent undesired
switching-onof the external MOS becauseof
some leakage current.
Pin 11. PGND (Power Ground). The current loop
during the dischargeof the gateof the external
MOSis closed through this pin. This loop should as short as possibleto reduce EMI and run
separatelyfrom signal currents return.
Pin 12. SGND (Signal Ground). This ground ref-
erences the control circuitryof the IC,so all the
ground connectionsof the external parts related control functions must leadto this pin.In laying
out the PCB, care must be takenin preventing
switched high currents from flowing through the
SGND path.
Pin 13. ISEN (Current Sense). This pinisto be
connectedto the ”hot” leadof the current sense
resistor Rsense (being the other one grounded),to
geta voltage ramp whichisan imageof the cur-
rentof the switch, (IQ). When this voltageis equal
to:
OUT Rg
DRIVE&
CONTROL
13VVCC
Rg’
PGND
Rg(ON)=Rg+Rg’
Rg(OFF)=Rg
D97IN497A
L4990
(V)
Figure25.Turn-onandturn-offspeedsadjustment SGND
OUT
VREFOK
D97IN538
Figure 26. Pull-Downof the outputin UVLO.
L4990- L4990A
12/24
