L4969 Fast Delivery |IC PHOENIX CO.,LIMITED

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L4969
SYSTEM VOLTAGE REGULATOR WITH FAULT TOLERANT LOW SPEED CAN-TRANSCEIVER
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L4969
September 2000 OPERATING SUPPLY VOLTAGE 6V TO 28V,
TRANSIENT UP TO 40V LOW QUIESCENT CURRENT
CONSUMPTION, LESS THAN 100μAIN
SLEEP MODE TWO VERY LOW DROP VOLTAGE
REGULATORS 5V/100mA AND 5V/200mA SEPARATE VOLTAGE REGULATOR FOR
CAN-TRANSCEIVER SUPPLY WITH LOW
POWER SLEEP MODE RESET LOGIC SERIAL INTERFACE CAN TRANSCEIVER (LOW SPEED, DOUBLE
WIRE) WITH FAULT TOLERANCE VOLTAGE SENSE COMPARATOR
DESCRIPTION
The L4969isan integrated circuit containing3 inde-
pendent Voltage Regulators anda standard fault tol-
erant low speed CAN line interfacein multipower
BCD3S process. integratesall main local functions for automotive
body electronic applications connectedtoa CAN
bus.
PRODUCT PREVIEW
SYSTEM VOLTAGE REGULATOR
WITH FAULT TOLERANT LOW SPEED CAN-TRANSCEIVER
Figure1. Block Diagram
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Figure2. Pin Connection
Table1. Pin Functions
Table2. Thermal Data
Note:1. Typical valuesolderedonaPCboardwith8cm2 copper ground plane (35μmthick).
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Table3. Absolute Maximum Ratings
Notes:1. The circuitis ESD protected accordingto MIL-STD-883C. Current forced means voltage unlimitedbut current limitedtothe specified value.
Voltage forced means voltage limitedtothe specified values whilethe currentisnot limited.
Table4. Electrical Characteristcs= 14V,Tj =-40°Cto150°C unless otherwise specified.
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Table4. Electrical Characteristcs (continued)
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Table4. Electrical Characteristcs (continued)
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Table4. Electrical Characteristcs (continued)
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Table4. Electrical Characteristcs (continued)
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Table4. Electrical Characteristcs (continued)
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1.0 FUNCTIONAL DESCRIPTION
1.1 General Features
The U435isa monolithic integrated circuit which providesall main functionsforan automotive body
CAN network. featurestwo independent regulated voltage suppliesV1 and V2,an interrupt and reset logicwith internal clock
generator, Serial Interface anda low speed CAN-bus transceiver whichis suppliedbya separate third voltage
regulator (V3).
The device guaranteesa clearly defined behaviorin caseof failure,to avoid permanent CAN bus errors.
The device operatesin three different modes: Sleep mode: V1isoffisoffisoff
CAN-Transceiver: active with reduced performance
Watchdog active
Table4. Electrical Characteristcs (continued)
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The total current consumptionis< 100μA. Standby mode: V1ison (μCin stop mode)isoffisoff
CAN-Transceiver: active with reduced performance
The total current consumptionis< 200μA. Operating mode: V1isonisonison Output Voltage
The V1 regulator usesa DMOS transistorasan output stage. With this structure very low dropout voltageat
currents upto 100mAis obtained.The dropout operation ofthe standby regulatoris maintained downto4V input
supply voltage. The output voltageis regulatedupto the transient input supply voltageof 40V. With this feature functional interruption dueto overvoltage pulsesis generated. The output1 regulatoris switchedoffin sleep
mode. Through metal option the output1 voltage canbe setto 3.3V. Output Voltage
TheV2 regulator uses the same output structureas the output1 regulator exceptto being short circuit proofto
VS, andtobe ratedfor the output currentof 200mA. TheV2 output canbe switchedon andoff througha ded-
icated enablebitin the control register.In additiona tracking option canbe enabledto allow V2 followV1 with
constant offset. This feature allows consistent A/D conversion inside the μC (suppliedby V1) when the convert- signals are referencedto V2. Output Voltage
The third voltage regulatorof the device generates the supply voltagefor the internal logic and the CAN-trans-
ceiver.In operating modeitis capableof supplyingupto 200mAin orderto guarantee the required short circuit
currentfor the CAN_H driver. The sleep and operating modes are switched througha dedicated enable bit.
Internal Supply Voltage low power sleep mode regulator supplies the internal logicin sleep mode.
1.2 CAN Transceiver Supports double wire unshielded busses Baud rateupto 125KBaud Short circuit protection (battery, ground, wires shorted) Single wire operation possible (automatic switchingto single wire upon bus failures) Bus not loadedin caseof unpowered transceiver
The CAN transceiver stageis ableto transfer serial dataon two independent communication wires either def-
erentially (normal operation)orin caseofa single wirefaulton the remaining line. The physical bitcodingis done
using dominant (transmitter active) and overwritable recessive states. Too long dominant phases are detected
internally and further transmissionis automatically disabled (malfunctionof protocol unit does not affect com-
municationon the bus, "fail-safe"- mechanism). For low current consumption during bus inactivitya sleep mode available. The operating mode canbe entered from the sleep mode eitherby local wakeup (μC)or upon de-
tectionofa dominantbiton the CAN-bus (external wake up).
Ten different errorson the physical buslines canbe distinguished:
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1.3 Detectable Physical Busline Failures
Notallof the10 different errors leadtoa breakdownof the whole communication. the errors canbe categorized into 'negligible', 'problematic' and 'severe':
Negligible Errors
Transmitter
ErrorI andII (CANHor CANL interrupted but still tiedto termination)
ErrorIV and VIII (CANHor CANL permanently dominantby short circuit)all cases above data can stillbe transmittedin differential mode.
Receiver
ErrorI andII (CANHor CANL interrupted but still tiedto termination)
ErrorV andIX (CANHor CANL permanently recessiveby short circuit)all cases above data can stillbe receivedin differential mode.
Problematic Errors
Transmitter
ErrorIII andVI (CANHor CANL show overvoltage conditionby short circuit)
Datais transmitted using the remaining dataline (single wire)
Receiver
ErrorIII andVI (CANHor CANL show overvoltage conditionby short circuit)
Datais received using the remaining dataline (single wire)
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Severe Errors
Transmitter
ErrorV andIX (CANHor CANL permanently recessiveby short circuit)
Datais transmittedon the remaining dataline after short circuit detection
ErrorVII (CANHis shortedto CANL)
Datais transmittedon CANHor CANL after overcurrent was detected
ErrorX (attemptto transmit more than10 successive dominant bits(at lowest bitrate specified)
Transmissionis terminated (fail safe)
Receiver
ErrorVII (CANHis shortedto CANL)
Datais receivedon CANHor CANL after detectionof permanent dominant state
ErrorIV and VIII (CANHor CANL permanently dominantby short circuit)
Datais receivedon CANHor CANL after short circuit was detected
ErrorX (receptionofa sequenceof dominant bits, violating the protocol rules)
Datais received normally, erroris detectedby protocol-unit
The error conditionsis signaled issuingan error flag insidea dedicated register whichis readableby the μC
through the serial interface. The informationof the error type(I throughX)is also stored into this register.
1.4 Oscillator low power oscillator providesan internal clock.In sleep mode (Watchdog active) the output frequencyis
250kHz,if the Watchdog functionis not requested, the internal Oscillatoris switched off. standby and operating mode the oscillatoris runningat 1MHz, and canbe calibratedina range from -16%to
+16% using the μC-XTALasa reference.
1.5 Watchdog triple function programmable watchdogis integratedto perform the following tasks: Wakeup Watchdog:
Whenin sleepor standby mode the watchdog can generatea wakeup condition aftera programma-
ble periodof time ranging from 80msupto45 minutes Startup Watchdog:
Upon V1 power-upor μC failure during SPI supervision (see SW-Watchdog)a reset pulseis gener-
ated periodically every 50ms for 2.5ms until activityof the μCis detected (SPI sequence)orno ac-
knowledgeis received within7 cycles (350ms).In this condition the deviceis forced into Sleep mode
untila Wakeupis detected anda startup cycleis reinitialized. Window Watchdog:
After passing the startup sequence, this watchdog requestan acknowledgeby the μCvia the SPI
withina programmable timing frame, ranging from 2.5... 5msupto20... 40ms. Upona missingor
misplaced acknowledge the Startup Watchdogis initialized.
1.6 Identifier Filter 12-Bit CAN-ID-filteris implemented allowing wakeup via specific CAN-messages thus aiding the implemen-
tationof low power partial communication networks like standby diagnostics without the needto power-up the
whole network. guarantee the detectionof the programmed Identifiers, the local RC-oscillator canbe calibratedto allow the
programmable Bittime logicto extract the incoming stream witha maximumof tolerance over temperature de-
viation.
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1.7 Power-on Reset
Upon Power-on (VS> 3.5V), the internal reset forces the device intoa predefined power-on state:onoffoff
CAN-Standby mode
ID-Filter disabled
Startup Watchdog active
With VS below5V the regulatorV1 will follow VS with minimum drop. The μC retrievesa resetifV1is dropping
belowa programmable voltage levelof either 4.5V(default)or 4.0V. The programmed stateof the U435 remains
unchanged.
1.8 Ground Shift Detection caseof single wire communicationvia CANH the signalto noise ratiois low. Detecting the local ground shift
canbe usedasan additional indicatoron the current signal quality. The informationof the integrated ground
shift detector willbe refreshed upon every falling edgeon TX and canbe read from the CAN Transceiver Status
Register (CTSR). willbe set,if V(CANH)< -1V, resetif V(CANH> -1V)at the falling edgeof TX.
1.9 Thermal Protection
The device features three independent thermal warning circuits which monitor the temperatureof theV1 output,
theV2 output and the CAN_H and CAN_L drivers together with voltage regulator V3. Each circuit setsa sepa-
rate overtemperature flagina register whichis read and writableby the serial interface. The overtemperature
flags causean interruptto the μC. The μCis able toswitch V1,V2 andCANdriverson andoff through dedicated
enable registers.To enhance system security following strategyis chosenfor thermal warning and shutdown:3 independent warning flags are setat 140°C for V1, V2 and V3/CAN-Transceiverat 170°C V2 and V3 switchedoffat 200°C V1is switchedoff V2 and V3 canbe switchedon again through the μC V1 canbe switchedon againat wake-up (Watchdog wake-up, CAN wake-up, external wake-up)
Note, thatifno wakeup sourceis setforV1a 1sec watchdog timeout willbe establishedto enablea proper retry
cycle.
1.10 Serial Interface (SPI) standard serial peripheral interface (SPI)is implementedto allow accessto the internal registersof the U435. totalof12 Registers with different datalengths canbe directly read fromor writtento, providing the requested
addressat thebeginning ofa dataframe. Upon every accessto this interface, the contentof the register currently
accessedis shifted out via SOUT.All operations are performedon the rising edgeof SCLK.Ifa frameis not
completed, the interfaceis automatically reset after 1.5msof SCLK idle time (auto timeout detection).
Dueto limited pin counton this device the chip select hastobe programmed explicitly (see Tristate SOUT) and
will returnto the normal output mode aftera fixed periodof 1.5ms after the last foreign SPI interaction.
The dataframe format used described below:
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General Dataframe Format:
Datais sampledon the rising edgeof the clock and SOUT will change upon SCLK falling. SOUT will showa
copyof SINfor the Address/Command fieldfor initial data path checks. Independentof the command state,
SOUT will show the contentof the register addressed. SIN contains either datatobe writtenor arbitrary data
forall other operations. The transaction willbe terminated with fourbitof data followedbya 4-Bit wide CRC
(Cyclic Redundancy Check)asa resultof either SIN related dataor calculated automaticallyon data returned
via SOUT. Here the μC hasto provide the correct sequencein orderto get the write command activated inside. CRC-failureis signalledvia NINT. For returned data the CRC can alsobe usedto verifya successful transfer.
Address/Command Field
The Address/Command field starts witha 2-Bit start sequence consistingof ‘01’. Any other sequence will leada protocol error signalled via the NINT. The addressfieldis specifying the registertobe accessed. The SPI
command flags allow inadditionto the normal read/write operation toeither cleara register after read (operating
onlyon IFR)orto disable SOUTto allow communication between μC and other peripherals using the sameSPI.
The SOUT functionis automatically reestablished after 1.5ms following the last transaction and willbe signalled
via NINT.
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Datafield#1
Datafield#1 contains either the lower8 bitsofa 12-Bit frameor the complete byteofan 8-Bit transfer.
Note, that SOUTis always showing the contentof the register currently accessed and nota copyof SINas dur-
ing the Address/Command field.
Datafield #2/CRC
Datafield#2 contains either the upper four bitsofa 12-Bit frameor zerosin caseofan 8-Bit transfer. This field followedbya fourbit CRC sequence thatis calculated based upon the polynom 0x11h (17 decimal). This
sequenceis simply the remainderofa polynomial division performedon the data previously transferred.If the
CRC appended totheSINsequencefails, any writing willbe disabled andan erroris signalled viaNINT. Another
remainderis calculatedon the SOUTstream and appended accordinglyto allow the application softwareto val-
idate the correctnessof incoming data.To aid evaluation, the CRC checking canbe turnedoffby writing arbi-
trary data witha valid CRCto address 15. CRC-checking willbe reenabled upon another operationof this kind
(Toggled information).

Partno	Mfg	Dc	Qty	Available	Descript
L4969	STM	N/a	40	avai	SYSTEM VOLTAGE REGULATOR WITH FAULT TOLERANT LOW SPEED CAN-TRANSCEIVER