L4922 Fast Delivery |IC PHOENIX CO.,LIMITED

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L4922
VERY LOW DROP REGULATOR WITH RESET
L4922
June 2000
VERY LOW DROP REGULATOR WITH RESET VERY LOW DROP (max. 0.9Vat1A) OVER
FULL OPERATINGTEMPERATURE RANGE40/+ 125°C). LOW QUIESCENT CURRENT (max 70 mAatA) OVER FULLT RANGE. PRECISE OUTPUT VOLTAGE(5V± 4%)
OVER FULLT RANGE. POWER ON-OFF INFORMATION WITH SET-
TABLEDELAY. REVERSE BATTERY PROTECTION. SHORT CIRCUIT PROTECTION. THERMAL SHUTDOWN
DESCRIPTION
The L4922isa highcurrentmonolithicvoltageregu-
lator with very low voltagedrop (0.70V maxat1A, =25 °C).
The deviceis internally protected against load
dumps transientof+ 60V, reverse polarity, over-
heatingandoutputshortcircuit: thankstotedforthe
automotive and industrial applications.
Pentawatt
ORDERING NUMBER: L4922
BLOCK DIAGRAM
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PIN CONNECTION (Top view)
FUNCTIONAL DESCRIPTION
The operating principleof the voltage regulatoris
basedon thereference,theerroramplifier,thedriver
and the power PNP. This stage uses an Isolated
CollectorVerticalPNP transistorwhich allowsto ob-
tain very low dropoutvoltage (typ. 450mV) and low
quiescentcurrent (IQ= 20mA typically atIo= 1A).
Thanksto these features the deviceis particularly
suited when the power dissipation mustbe limited
as,for example,in automotiveor industrialapplica-
tions suppliedby battery.
The three gain stages (operational amplifier,
driver andpower PNP) require the external capaci-
tor (Comin =22μF)to guaranteethe global stability the system.
Theantisaturationcircuitallowstoreducedrastically
the current peak which takes place during the start
up.
The reset functionis LOW active when the output
voltage levelis lower than the reset threshold volt-
ageVRthOFF (typ.value:Vo –150mV).Whentheout-
put voltageis higherthanVRthON theresetbecomes
HIGHaftera delaytimesettablewiththeexternalca-
pacitorCd. Typicallytd =20ms,Cd =0.1μF.The reset
and delay threshold hysteresis improve the noise
immunity allowingto avoid false switchings. The
typical reset outputwaveformis shownin fig.1.
ABSOLUTE MAXIMUM RATINGS
Symbol Parameter Value Unit DC Input Voltage 35 V DC Reverse Voltage –18 V Positive Load Dump Protection(t= 300ms) 60 V Junction Temperature Range –40to 150 °C
Top Operating Temperature Range –40to 125 °C
Tstg Storage Temperature Range –55to 150 °C
THERMAL DATA
Symbol Parameter Value Unit
Rth j-case Thermal Resistance Junction-case Max. 3.5 °C/W
Note: The circuitis ESD protected accordingto MIL-STD-883C
L4922
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ELECTRICAL CHARACTERISTICS(Vi= 14.4V,– 40°C≤TJ≤+ 125°C unless otherwise specified)
Symbol Parameter Test Conditions Min. Typ. Max. Unit Operating Input Voltage (*) Note1 6 26 V Output Voltage Io= 0mAto1A =25°C
ΔVLine Line Regulation Vi=6to 26V; IO= 10mA 5 25 mV
SVR Supply Voltage Rejection Io= 700mA= 120Hz;Co =47μF= 12Vdc +5Vpp dB
ΔVLOAD Load Regulation Io= 10mAto1A 15 50 mV –Vo Dropout Voltage TJ =25°C,IO =1A 0.45 0.70 V
Over FullT,Io=1A 0.90 V Quiescent Current Io= 10mA =1A
ISC Short Circuit Current 1.8 A Rset Output Saturation Voltage 1.5VVRT peak Power On-Off Reset out Peak
Voltage
1KΩ Reset Pull-uptoVO 0.65 1.0 V Reset Output Leakage Current
(high level)in Regul. =5V μA Reset Pulse Delay Time CD= 100nF 20 ms
VRthOFF Power OFFVo Threshold Vo@ Reset outHtoL
Transition;TJ =25°C
–40°C≤TJ≤+ 125°C
4.70 –0.15 V
IC6 Delay Capacitor Charging
Current (current generator) =3V 20 μA
VRthON Power ONVo Threshold Vo@ Reset outLtoH
Transition
VrthOFF 0.03V–
0.04V Delay Comparator Threshold Resetout=”1”HtoL Transition 3.2 3.8 V
Resetout=”0”LtoH Transition 3.7 4 4.4 V
V6H Delay Comparator Hysteresis 500 mV
(*)Note1: The deviceis notoperating withintherange:26VEXTERNAL COMPENSATION
Sincethe purposeofa voltageregulatoristo supply fixed output voltagein spiteof supply and load
variations,the open loopgainof the regulatormust very highat low frequencies.Thismay causein-
stabilityasa resultof the various poles presentin
the loop. To avoid this instability dominant pole
compensationis usedtoreducephase shiftsdueto
other polesat the unity gain frequency. The lower
thefrequencyoftheseotherpoles,the greater must the capacitor usedto create the dominant pole
for the same DC gain.
Where the output transistorisa lateral PNP type
thereisa polein the regulation loopata frequency
toolowtobe compensatedbya capacitorwich can integrated. An external compensationis there-
fore necessarysoa very high value capacitor must connected from the outputto ground.
Theparassiticequivalentseriesresistanceof theca-
pacitorusedaddsa zeroto the regulation loop.This
zero may compromise the stabilityof the system
sinceits effecttendsto cancel the effectof the pole
added.In regulatorsthis ESR mustbe less than 3Ω
and theminimum capacitor value is47μF.
L4922
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Figure1: Typical Reset OutputWaveform.
Figure2: TypicalApplication Circuit.
(*) RECOMMENDED VALUE:C0 =47 μF, ESR<10 ohm, (Iout>10 mA) OVER FULLTrange.
L4922
4/6
PentawattV
DIM. mm inch
MIN. TYP. MAX. MIN. TYP. MAX. 4.8 0.189 1.37 0.054 2.4 2.8 0.094 0.110 1.2 1.35 0.047 0.053 0.35 0.55 0.014 0.022 0.76 1.19 0.030 0.047 0.8 1.05 0.031 0.041 1 1.4 0.039 0.055 3.2 3.4 3.6 0.126 0.134 0.142 6.6 6.8 7 0.260 0.268 0.276 10.4 0.409 10.05 10.4 0.396 0.409 17.55 17.85 18.15 0.691 0.703 0.715 15.55 15.75 15.95 0.612 0.620 0.628 21.2 21.4 21.6 0.831 0.843 0.850 22.3 22.5 22.7 0.878 0.886 0.894 1.29 0.051 2.6 3 0.102 0.118 15.1 15.8 0.594 0.622 6 6.6 0.236 0.260 0.2 0.008 4.23 4.5 4.75 0.167 0.177 0.187 3.75 4 4.25 0.148 0.157 0.167 40° (typ.) L2D
Dia. H2
GG1
RESIN BETWEEN
LEADSV1
OUTLINE AND
MECHANICAL DATA
L4922
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Partno	Mfg	Dc	Qty	Available	Descript
L4922	ST	N/a	10	avai	VERY LOW DROP REGULATOR WITH RESET