SN54HC174J ,Hex D-type Flip-Flops With Clearmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN54HC175J ,Quadruple D-type Flip-Flops With Clearmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN54HC191J ,Synchronous 4-Bit Up/Down Binary Counters SCLS121D − DECEMBER 1982 − REVISED OCTOBE ..
SN54HC193J ,Synchronous 4-Bit Up/Down Binary Counters With Dual Clock And Clear/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN54HC195J ,4-Bit Parallel-Access Shift Registers 16-CDIP -55 to 125maximum ratings" may cause permanent damage to the device. These are stress ratingsonly, and functi ..
SN54HC20J ,Dual 4-Input Positive-NAND Gatesmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74F245 ,Octal bus transceivers SN54F245, SN74F245 OCTAL BUS TRANSCEIVERS WITH 3-STATE OUTPUTSSDFS010A – MARCH 1987 – REVISED OCTO ..
SN74F245DBR ,Octal bus transceiversmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74F245DW ,Octal bus transceiversmaximum ratings” may cause permanent damage to the device. These are stress ratings only andfunctio ..
SN74F245DWR ,Octal bus transceiversmaximum ratings” may cause permanent damage to the device. These are stress ratings only andfunctio ..
SN74F245N ,Octal bus transceiversmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN74F245NSR ,Octal bus transceiverslogic diagram (positive logic)191OE G3 DIR1DIR 3EN1[BA]193EN2[AB] OE2 18A1 1 B1 2A123 17A2 B2184 16 ..
JM38510/65307BEA-SN54HC174J-SNJ54HC174J
Hex D-type Flip-Flops With Clear
±4-mA Output Drive at 5 V
Low Input Current of 1 µA Max Contain Six Flip-Flops With Single-RailOutputs Applications Include:
− Buffer/Storage Registers
− Shift Registers
− Pattern Generators
description/ordering informationThese positive-edge-triggered D-type flip-flops
have a direct clear (CLR) input.
Information at the data (D) inputs meeting the
setup time requirements is transferred to the
outputs on the positive-going edge of the clock
(CLK) pulse. Clock triggering occurs at a
particular voltage level and is not directly related
to the transition time of the positive-going edge of
CLK. When CLK is at either the high or low level,
the D input has no effect at the output.
ORDERING INFORMATION†Package drawings, standard packing quantities, thermal data, symbolization, and PCB design guidelines are
available at www.ti.com/sc/package.
SN54HC174...FK PACKAGE
(TOP VIEW)CLRNC
CLK
GND
GND
CLK
NC − No internal connection
