SN54HC74J ,Dual D-type Positive-Edge-Triggered Flip-Flops With Clear And PresetFeatures 3 DescriptionThe SNx4HC74 devices contain two independent D-1• Wide Operating Voltage Rang ..
SN54HC86J ,Quadruple 2-Input Exclusive-OR Gates/sc/package.Please be aware that an important notice concerning availability, standard warranty, an ..
SN54HCT02J , QUADRUPLE 2-INPUT POSITIVE-NOR GATES
SN54HCT04J ,Hex Invertersmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
SN54HCT125J , QUADRUPLE BUS BUFFER GATES WITH 3-STATE OUTPUTS
SN54HCT138J ,3-Line To 8-Line Decoders/Demultiplexersmaximum ratings” may cause permanent damage to the device. These are stress ratings only, andfuncti ..
SN74F352N ,Dual 4-line to 1-line data selectors / multiplexers 16-PDIP 0 to 70
SN74F373 ,Octal D-type transparent latcheselectrical characteristics over recommended operating free-air temperature range (unlessotherwise n ..
SN74F373DB , OCTAL TRANSPARENT D-TYPE LATCHES WITH 3-STATE OUTPUTS
SN74F373DBR ,Octal D-type transparent latchesmaximum ratings” may cause permanent damage to the device. These are stress ratings only andfunctio ..
SN74F373DBR ,Octal D-type transparent latcheslogic diagram (positive logic)11OE ENOE11LE C111LE3 21D 1D 1Q4 5C12D 2Q21Q7 633D 3Q 1D 1D8 94D 4Q13 ..
SN74F373DW ,Octal D-type transparent latchesmaximum ratings over operating free-air temperature range (unless otherwise noted)Supply voltage ra ..
JM38510/65302B2A-JM38510/65302BCA-SN54HC74J-SNJ54HC74J-SNJ54HC74W
Dual D-type Positive-Edge-Triggered Flip-Flops With Clear And Preset
PRE
CLK
CLR TG TGProduct
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SN54HC74, SN74HC74SCLS094E –DECEMBER 1982–REVISED DECEMBER 2015
SNx4HC74 Dual D-Type Positive-Edge-Triggered Flip-Flops With Clear and Preset Features 3 DescriptionThe SNx4HC74 devices contain two independent D- Wide Operating Voltage Range:2Vto6V type positive-edge-triggered flip-flops.A low levelat• Outputs Can Drive Up To10 LSTTL Loads the preset (PRE)or clear (CLR) inputs setsor resets• Low Power Consumption, 40-µA Maximum ICC the outputs, regardless of the levels of the other
inputs. When PRE and CLR are inactive (high), data• Typicaltpd= 15ns at the data (D) input meeting the setup time• ±4-mA Output Driveat5V requirements are transferredto the outputs on the• Very Low Input Currentof1 µA positive-going edgeof the clock (CLK) pulse. Clock
triggering occursata voltage level andis not directly
2 Applications relatedto the rise timeof CLK. Following the hold-
time interval, dataat theD input can be changed• Ultrasound System without affecting the levelsat the outputs.• Fans Lab Instrumentation
Device Information(1)• Vacuum Cleaners• Video Communications System• IP Phone: Wired
(1) Forall available packages, see the orderable addendumat
the endofthe data sheet.
Logic Diagram (Positive Logic)
