JM38510/01701BEA ,Hex D Flip-Flop with ClearApplications include:requirements is transferred to the Q outputs on the positive-Buffer/storage re ..
JM38510/05001BCA ,CMOS Quad 2-Input NAND GateMAXIMUM RATINGS, Absolute-Maximum Values:STORAGE-TEMPERATURE RANGE (T519). _ _OPERATING-TEMPERATURE ..
JM38510/05051BCA ,CMOS Quad 2-Input NAND Gatelogic diagrams for 6040128.Vonst I J " H>r-' Autur rmvnnun: (w . ereq18,ltt- GISJO)s’tmn3'IB,1st-Pu ..
JM38510/05053BCA ,CMOS Triple 3-Input NAND Gate0040113, CD40123, 0040233 TypesCMOS NAND GATESHigh-Voltage Types (20-Volt Rating)
JM38510/05151BCA ,CMOS Dual D-Type Flip FlopSample & Support &Product Tools &TechnicalCommunityBuyFolder Documents SoftwareCD4013BSCHS023E–NOVE ..
JM38510/05152BEA ,CMOS Dual J-K Master-Slave Flip-FlopMAXIMUM RATINGS, Absolute-Maximum Values: aesnz d cum:Dc SUPPLY-VOLTAGE RANGE, (V00) I' i m!"Voltag ..
KA2135 , HORIZONTAL SIGNAL PROCESSING
KA2142 ,Vertical Deflection Output CircuitKA2142Vertical Deflection Output Circuit
KA2142C ,Vertical Output ICKA2142CVertical Deflection Output Circuit
KA2155 , LINEAR INTEGRATED CIRCUIT
KA2155 , LINEAR INTEGRATED CIRCUIT
KA2202 , LOW VOLTAGE DC MOTOR SPEED CONTROLLER
JM38510/01701BEA
Hex D Flip-Flop with Clear
TL/F/6557
54174/DM54174/DM74174,
54175/DM54175/DM74175
Hex/Quad
Flip-Flops
with
Clear
June 1989
54174/DM54174/DM74174, 54175/DM54175/DM74175
Hex/QuadD Flip-Flops with Clear
General Description
These positive-edge triggered flip-flops utilize TTL circuitry implement D-type flip-flop logic.All havea direct clear
input,andthe quad (175) version features complementary
outputs from each flip-flop.
InformationattheD inputs meetingthe setupand hold time
requirementsis transferredto theQ outputsonthe positive-
going edgeofthe clock pulse. Clock triggering occursata
particular voltage levelandisnot directly relatedtothe tran-
sition timeofthe positive-going pulse. Whenthe clock inputat eitherthe highorlow level,theD input signalhasno
effectatthe output.
Features 174 containssix flip-flops with single-rail outputs 175 contains four flip-flops with double-rail outputs Buffered clockand direct clear inputs Individual data inputto each flip-flop Applications include:
Buffer/storage registers
Shift registers
Pattern generators Typical clock frequency40 MHz Typical power dissipationper flip-flop38 mW Alternate Military/Aerospace device (54174, 54175)is
available. Contacta National Semiconductor SalesOf-
fice/Distributorfor specifications.
Connection Diagrams
Dual-In-Line Package
TL/F/6557–1
Order Number 54174DMQB, 54174FMQB, DM54174J,
DM54174Wor DM74174N
SeeNS Package Number J16A, N16Eor W16A
Dual-In-Line Package
TL/F/6557–2
Order Number 54175DMQB, 54175FMQB,DM54175J,
DM54175Wor DM74175N
SeeNS Package Number J16A, N16EorW16A
Function Table (EachFlip-Flop)
Inputs Outputs
Clear Clock D Q Q² X L H u HH L u LL H X Q0 Q0eHigh Level (steady state)eLow Level (steady state)e Don’tCaree Transitionfrom lowtohighleveleThe levelofQ beforethe indicated steady-stateinput conditionswere established.e175only
C1995National SemiconductorCorporation RRD-B30M105/PrintedinU.S.A.
