IRS2112STRPBF ,High and Low Side Driver, Shutdown InputFeaturesProduct Summary• Floating channel designed for bootstrap operation• Fully operational to +6 ..
IRS2113 ,High and Low Side Driver, All High Voltage Pins On One Side, Separate Logic and Power Ground, Shut-Down and High Creepageelectrical characteristics are measured using the test circuit shown in Fig. 3.Symbol Definition Mi ..
IRS2113 ,High and Low Side Driver, All High Voltage Pins On One Side, Separate Logic and Power Ground, Shut-Down and High Creepageapplications.The floating channel can be used to drive an N-channel16-Lead SOIC14-Lead PDIPIRS2110S ..
IRS2113PBF , HIGH AND LOW SIDE DRIVER
IRS2113SPBF , HIGH AND LOW SIDE DRIVER
IRS2113STRPBF ,High and Low Side Driver, All High Voltage Pins On One Side, Separate Logic and Power Ground, Shut-Down and High CreepageElectrical CharacteristicsV (V , V , V ) = 15 V, C = 1000 pF, T = 25 °C and V = COM unless otherwis ..
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IRS2112-IRS2112STRPBF
High and Low Side Driver, Shutdown Input
Data Sheet No. PD60251
International
ISBR Rectifier IRS2112(-1,-2,S)PbF
HIGH AND LOW SIDE DRIVER
Featu res
. Floating channel designed for bootstrap operation Product Summary
q Fully operational to +600 V
. Tolerant to negative transient voltage, dV/dt VOFFSET 600 V max.
Immune
q Gate drive supply range from 10 V to 20 V kyr/- 200 mA / 440 mA
. Undervoltage lockout for both channels
. 3.3 V logic compatible VOUT 10 V - 20 V
q Separate logic supply range from 3.3 V to 20 V
. Logic and power ground +/- 5 V offset ton/off (typ.) 135 ns & 105 ns
I CMOS Schmitt-triggered inputs with pull-down
q Cycle by cycle edge-triggered shutdown logic Delay Matching 30 ns
. Matched propagation delay for both channels
I Outputs in phase with inputs Packages
q RoHS compliant
Description 14-t.ead PDIP
. . . IRS2112 l
The IRS2112 IS a high voltage, high speed power 16-tead PDIP ll
MOSFET and IGBT driver with independent high- and (w/o leads 4 & 5)
IRS2112-2
Iow-side referenced output channels. Proprietary HVIC
and latch immune CMOS technologies enable rug- 14-Lead PDIP
gedized monolithic construction. Logic inputs are com- (w/o lead 4)
patible with standard CMOS or LSTTL outputs, down fig IRS2112-1
to 3.3 V logic. The output drivers feature a high pulse l; i _ x
. . . . I I 16-Lead SOIC
current buffer stage designed for minimum driver "I IRS2112S
cross-conduction. Propagation delays are matched
to simplify use in high frequency applications. The
floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side configuration
which operates up to 600 V.
. . u to 600 V
Typical Connection p -
- HO " KN
Va, OT Vor, VB L
HIN o—"\— HIN vs T o TO
SD o—— SD - E oLOAD
LIN o—— LIN Vcc i
Vss Cr-4F--- Vss COM T I Er
Vcc - LO W»
(Refer to Lead Assignments for correct pin configuration). This diagram shows electrical connections only. Please ==
refer to our Application Notes and DesignTips for proper circuit board layout.
1
International IRS2112(-1,-2,S)PbF
TOR Rectifier
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in Figs. 28 through 35.
Symbol Definition Min. Max. Units
VB High-side floating supply voltage -0.3 625
Vs High-side floating supply offset voltage VB - 25 VB + 0.3
VH0 High-side floating output voltage Vs - 0.3 VB + 0.3
va, Low-side fixed supply voltage -0.3 25 V
VLo tDw-side output voltage -0.3 Vcc + 0.3
VDD logic supply voltage -O.3 VSS + 25
Vss Logic supply offset voltage Vcc - 25 Vcc + 0.3
VIN Logic input voltage (HIN, LIN & SD) vss - 0.3 VDD +0.3
st/dt Allowable offset supply voltage transient (Fig. 2) - 50 V/ns
. F . (14 Lead DIP) - 1.6
PD Package power dissipation @ TA 3 +25 "C (16 Lead SOIC) - 1.25 W
(14 Lead DIP) - 75
RTHJA Thermal resistance, junction to ambient °C/W
(16 Lead SOIC) - 100
TJ Junction temperature - 150
Ts Storage temperature -55 150 "C
TL Lead temperature (soldering, 10 seconds) - 300
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. l. For proper operation the device should be used within the
recommended conditions. The vs and Vss offset ratings are tested with all supplies biased at 15 V differential. Typical
ratings at other bias conditions are shown in Figs. 36 and 37.
Symbol Definition Min. Max. Units
VB High-side floating supply absolute voltage Vs + 10 Vs + 20
Vs High-side floating supply offset voltage Note 1 600
VH0 High-side floating output voltage vs VB
ve Low-side fixed supply voltage 10 20
VLo Cow-side output voltage 0 Vcc V
VDD Logic supply voltage Vss + 3 VSS + 20
vss Logic supply offset voltage -5 (Note 2) 5
VIN Logic input voltage (HIN, LIN & SD) VSS VDD
TA Ambient temperature -40 125 ''C
Note 1: Logic operational for vs of -5 V to +600 V. Logic state held for vs of -5 V to IBS. (Please refer to the Design
Tip DT97-3 for more details).
Note 2: When VDD < 5 V, the minimum Vss offset is limited to A/DD.
2
