IRS2111STRPBF ,Half Bridge Driver, Fixed 650ns Deadtime in a 8-Lead packageapplications. Propri-etary HVIC and latch immune CMOS technologies enableruggedized monolithic cons ..
IRS2112 ,High and Low Side Driver, Shutdown Inputapplications. Thefloating channel can be used to drive an N-channel power MOSFET or IGBT in the hi ..
IRS2112PBF , HIGH AND LOW SIDE DRIVER
IRS2112STRPBF ,High and Low Side Driver, Shutdown InputFeaturesProduct Summary• Floating channel designed for bootstrap operation• Fully operational to +6 ..
IRS2113 ,High and Low Side Driver, All High Voltage Pins On One Side, Separate Logic and Power Ground, Shut-Down and High Creepageelectrical characteristics are measured using the test circuit shown in Fig. 3.Symbol Definition Mi ..
IRS2113 ,High and Low Side Driver, All High Voltage Pins On One Side, Separate Logic and Power Ground, Shut-Down and High Creepageapplications.The floating channel can be used to drive an N-channel16-Lead SOIC14-Lead PDIPIRS2110S ..
ISPLSI5256VA , In-System Programmable 3.3V SuperWIDE™ High Density PLD
ISPLSI5256VA-100LQ208 , In-System Programmable 3.3V SuperWIDE™ High Density PLD
ISPLSI5256VA-125LB208 , In-System Programmable 3.3V SuperWIDE™ High Density PLD
ISPLSI5256VA-125LB272 , In-System Programmable 3.3V SuperWIDE™ High Density PLD
ISPLSI5256VA-125LB272 , In-System Programmable 3.3V SuperWIDE™ High Density PLD
ISPLSI5256VA-70LB272I , In-System Programmable 3.3V SuperWIDE™ High Density PLD
IRS2111-IRS2111STRPBF
Half Bridge Driver, Fixed 650ns Deadtime in a 8-Lead package
International
TOR Rectifier
Data Sheet No. PD60253
IRS2111(S)PbF
Features
q Floating channel designed for bootstrap operation
q Fully operational to +600 V
q Tolerant to negative transient voltage, dV/dt
immune
q Gate drive supply range from 10 V to 20 V
q Undervoltage lockout for both channels
q CMOS Schmitt-triggered inputs with pull-down
q Matched propagation delay for both channels
q Internally set deadtime
q High-side output in phase with input
q RoHS compliant
Description
The IRS2111 is a high voltage, high speed power MOSFET and
IGBT driver with dependent high-side and Iow-side referenced
output channels designed for half-bridge applications. Propri-
etary HVIC and latch immune CMOS technologies enable
ruggedized monolithic construction. Logic input is compatible
with standard CMOS outputs. The output drivers feature a high
pulse current buffer stage designed for minimum driver cross-
HALF-BRIDGE DRIVER
Product Summary
VOFFSET 600 V max.
Io+/- 200 mA / 420 mA
VOUT 10 V - 20 V
ton/off (typ.) 750 ns & 150 ns
Deadtime (typ.) 650 ns
Packages
conduction. Internal deadtime is provided to avoid shoot-through ttr/l),',', 8-tead SOIC
in the output half-bridge. The floating channel can be used to IRS21111SPbF
drive an N-channel power MOSFET or IGBT in the high-side con-
figuration which operates up to 600 V.
Typical Connection
upto 600V
(Refer to Lead Assignments for correct pin configuration). This diagram shows electrical connections only. Please
refer to our Application Notes and DesignTips for propercircuit board layout.
International IRS2111(S)PbF
TOR Rectifier
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in Figs. 7 through 10.
Symbol Definition Min. Max. Units
VB High-side floating supply voltage -0.3 625 (Note 1)
Vs High-side floating supply offset voltage VB - 25 VB + 0.3
VH0 High-side floating output voltage Vs - 0.3 VB + 0.3
Vcc Low-side and logic foted supply voltage -0.3 25 (Note 1) V
VLo [.ow-side output voltage -0.3 Vcc + 0.3
VIN Logic input voltage -0.3 VCC + 0.3
st/dt Allowable offset supply voltage transient (Fig. 2) - 50 V/ns
PD Package power dissipation @ TA 5 +25 ''C (8 Lead PDIP) - 1.0 W
(8 lead SOIC) - 0.625
RthJA Thermal resistance, junction to ambient (8 lead PDIP) - 125 °CNV
(8 lead SOIC) - 200
TJ Junction temperature - 150
Ts Storage temperature -55 150 ''C
TL Lead temperature (soldering, 10 seconds) - 300
Note 1: All supplies are fully tested at 25 V, and an internal 20 V clamp exists for each supply
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. The Vs offset rating is tested with all supplies biased at a 15 V differential.
Symbol Definition Min. Max. Units
VB High-side floating supply absolute voltage Vs + 10 Vs + 20
Vs High-side floating supply offset voltage Note 2 600
VH0 High-side floating output voltage Vs VB V
Vcc Low-side and logic fixed supply voltage 10 20
VLo Low-side output voltage 0 Vcc
MN Logic input voltage 0 Vcc
TA Ambient temperature -40 125 ''C
Note 2: Logic operational for Vs of -5 V to +600 V. Logic state held for Vs of -5 V to A/BS. (Please refer to the Design Tip
DT97-3 tor more details).
2
