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IRS2110-IRS2110STRPBF-IRS2113-IRS2113STRPBF
High and Low Side Driver, All High Voltage Pins On One Side, Separate Logic and Power Ground, Shut-Down, High Creepage
Data Sheet No. PD60249
International
r R ifi IRS21'10(-1,-2,S)PbF
TOR ecti lei IRS2113(-1,-2,S)PbF
HIGH AND LOW SIDE DRIVER
Features
q Floating channel designed for bootstrap operation Product Summary
q Fully operational to +500 V or +600 V VOFFSET (IRS2110) 500 V max.
q Tolerant to negative transient voltage, dV/dt immune (IRS2113) 600 V max.
q Gate drive supply range from 10 V to 20 V
q Undervoltage lockout for both channels lO+/- 2 A/2 A
q 3.3 V logic compatible VOUT 10 V - 20 V
q Separate logic supply range from 3.3 V to 20 V
q Logic and power ground 15V offset ton/off (typ.) 130 ns & 120 ns
q CMOS Schmitt-triggered inputs with pull-down Delay Matching (IRS2110) 10 ns max.
q Cycle by cycle edge-triggered shutdown logic (IRS2113) 20 ns max.
q Matched propagation delay for both channels
q Outputs in phase with inputs Packages
q RoHS compliant
Description
The lRS2110/lRS2113 are high voltage, high speed
power MOSFET and IGBT drivers with independent
hig h-side and low-side referenced output channels. Pro-
prietary HVIC and latch immune CMOS technologies 14-Lead PDIP 1/5'II-eag 'ell
enable ruggedized monolithic construction. Logic in- IRS2110 and IRS2113 IRS2(1V:8-ze:n: |R82)113_2
puts are compatible with standard CMOS or LSTTL out-
put, down to 3.3 V logic. The output drivers feature a $35.
high pulse current buffer stage designed for minimum " [ \¢\
driver cross-conduction. Propagation delays are l " C
matched to simplify use in high frequency applications. I _
The floating channel can be used to drive an N-channel 14-Lead PDIP 16-read SOIC
power MOSFET or IGBT in the high-side configuration (w/o lead 4) IRS2110S and
which operates up to 500 V or 600 V. lRS2110-1 and IRS2113-1 IRS2113S
Typical Connection up to 500_V_or 600 V
- HO " _
VDD o t VDD Vs l
HIN o HIN Vs "T" 0 TO
SD 0 SD - E OLOAD
LIN o LIN Vcc 1
Vss c Vss COM - l "
Vcc - LO
(Refer to Lead Assignments for correct pin configuration). This diagram shows electrical connec- ==
tions only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
1
International
TOR Rectifier IRS2110(-1,-2,S)PbFllRS2113(-1,-2,S)PbF
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in Figs. 28 through 35.
Symbol Definition Min. Max. Units
(IRS2110) -O.3 520 (Note 1)
VB High-side floating supply voltage
(IRS2113) -0.3 620 (Note 1)
Vs High-side floating supply offset voltage VB - 20 " + 0.3
VH0 High-side floating output voltage Vs - 0.3 " + 0.3
Vcc tow-side fixed supply voltage -0.3 20 (Note 1) V
VLO Low-side output voltage -0.3 VCC + 0.3
VDD Logic supply voltage -0.3 VSS+20
(Note 1)
VSS Logic supply offset voltage VCC - 20 VCC + 0.3
VIN Logic input voltage (HIN, LIN, & SD) VSS - 0.3 VDD +0.3
st/dt Allowable offset supply voltage transient (Fig. 2) - 50 V/ns
(14 lead DIP) - 1.6
PD Package power dissipation © TA S +25 °C (16 lead SOIC) - 1.25 W
. . . . (14 lead DIP) - 75
RTHJA Thermal resistance, junction to ambient °C/W
(16 lead SOIC) - 100
TJ Junction temperature - 150
Ts Storage temperature -55 150 ''C
Tr, Lead temperature (soldering, 10 seconds) - 300
Note 1: All supplies are fully tested at 25 V, and an internal 20 V clamp exists for each supply.
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation, the device should be used within the
recommended conditions. The vs and Vss offset ratings are tested with all supplies biased at a 15 V differential.
Typical ratings at other bias conditions are shown in Figs. 36 and 37.
Symbol Definition Min. Max. Units
VB High-side floating supply absolute voltage Vs + 10 vs + 20
. . . (IRS2110) Note 2 500
vs High-side floating supply offset voltage
(IRS2113) Note 2 600
VH0 High-side floating output voltage vs VB
Vcc tow-side fixed supply voltage 10 20 V
VLO Low-side output voltage 0 V00
V00 Logic supply voltage VSS + 3 VSS + 20
Vss Logic supply offset voltage -5 (Note 3) 5
VIN Logic input voltage (HIN, LIN & SD) I/ss VDD
TA Ambient temperature -40 125 ''C
Note 2: Logic operational for vs of -4 V to +500 V. Logic state held for vs of -4 V to NBS. (Refer to the Design Tip DT97-3)
Note 3: When VDD < 5 V, the minimum VSS offset is limited to IDD.
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