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IRS2011-IRS2011STRPBF
High and Low Side Driver
Data Sheet No.P060221
International
TGiR 'Uctifier IRS2011(S)PbF
HIGH AND LOW SIDE DRIVER
Features
. Floating channel designed for bootstrap operation Product Summary
. Fully operational up to +200 V
. Tolerant to negative transient voltage, dV/dt immune VOFFSET 200 V max.
. Gate drive supply range from 10 V to 20 V
. Independent Iow-side and high-side channels
. Input logic HlN/LIN active high kr-l- 1.0 A/1.0 A typ.
. Undervoltage lockout for both channels
. 3.3 V and 5 V input logic compatible VOUT 10 V - 20 V
. CMOS Schmitt-triggered inputs with pull-down
. Matched propagation delay for both channels ton/off 60 ns typ.
. RoHS com liant .
. _p Delay Matching 20 ns max.
Applications
. Audio Class D amplifiers P k
. High power DC-DC SMPS converters ac ages
. DC motor drive
Description otitliiiiii,,is
The IRS2011 is a high power, high speed power MOSFET 'or/iii'''''''
driver with independent high and low-side referenced output
channels, ideal for Audio Class D and DC-DC converter appli- IR82011 IRS2011S
cations. Logic inputs are compatible with standard CMOS or 8-Lead PDIP 8-Lead SOIC
LSTTL output, down to 3.3 V logic. The output drivers feature a
high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are
matched to simplify use in high frequency applications. The floating channel can be used to drive an N-
channel power MOSFET in the high-side configuration which operates up to 200 V. Proprietary HVIC and
latch immune CMOS technologies enable ruggedized monolithic construction.
Typical Connection 200 v
HIN HIN Vs -1- /\
LIN 0— LIN HO cl.., JVVV
VB T 0 TO
COM COM LOAD
8 LO ,"'""h Vcc 1
Vcc cr- g; C', Ill l
(Refer to Lead Assignments for correct configuration). This diagram shows electrical connections only.
Please refer to our Application Notes and DesignTips for proper circuit board layout.
1
International
IDR Rectifier
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
IRS2011(S)PbF
Symbol Definition Min. Max. Units
VB High-side floating supply voltage -0.3 220 (Note 1)
Vs High-side floating supply offset voltage VB - 20 VB + 0.3
VH0 High-side floating output voltage Vs - 0.3 VB + 0.3
VCC Low-side fixed supply voltage -0.3 20 (Note 1) V
VLo Low-side output voltage -0.3 VCC +0.3
VIN Logic input voltage (HIN & LIN) -0.3 VCC +0.3
st/dt Allowable offset supply voltage transient (Fig. 2) - 50 V/ns
PD Package power dissipation @ TA = +25 ''C (8-lead DIP) - 1.0 W
(8-lead SOIC) - 0.625
. . . . (8-lead DIP) - 125
RTHJA Thermal resistance, junction to ambient °C/W
(8-lead SOIC) - 200
TJ Junction temperature - 150
Ts Storage temperature -55 150 ''C
TL Lead temperature (soldering, 10 seconds) - 300
Note 1: All supplies are fully tested at 25 V and an internal 20 V clamp exists for each supply.
Recommended Operating Conditions
For proper operation the device should be used within the recommended conditions. The vs and COM offset ratings
are tested with all supplies biased at a 15 V differential.
Symbol Definition Min. Max. Units
VB High-side floating supply absolute voltage Vs + 10 VS + 20
Vs High-side floating supply offset voltage Note 2 200
VH0 High-side floating output voltage Vs VB
VCC Low-side fixed supply voltage 10 20 V
VLo Low-side output voltage 0 Vcc
VIN Logic input voltage (HIN & LIN) COM 5.5
TA Ambient temperature -40 125
Note 2: Logic operational for Vs of -5 V to +200 V. Logic state held for vs of -5 V to -VBs.
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