IRS2004STRPBF ,Half Bridge Driver, high speed power MOSFET and IGBT drivers with dependent high and low side referenced output channels Data Sheet No.PD60270IRS2004(S)PbFHALF-BRIDGE DRIVER
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IRS2004-IRS2004SPBF-IRS2004STRPBF
Half Bridge Driver, high speed power MOSFET and IGBT drivers with dependent high and low side referenced output channels
l n Te rn Cl ti (D n C) I Data Sheet No.PD60270
ISQR Rectifier IRS2004(S)PbF
HALF-BRIDGE DRIVER
Features Product Summary
0 Floating channel designed for bootstrap operation
q Fully operational to +200 V VOFFSET 200 V max.
q Tolerant to negative transient voltage, dV/dt
immune kyr/- 130 mA/270 mA
q Gate drive supply range from 10 V to 20 V
q Undervoltage lockout
VOUT 10 V - 20 V
q 3.3 V, 5 V, and 15 V input logic compatible t t 680 ns 150 ns
q Cross-conduction prevention logic on/off( yp.) /
q Internally set deadtime Deadtime (typ.) 520 ns
q High-side output in phase with input
q Shutdown input turns off both channels
q Matched propagation delay for both channels Packages
q RoHS compliant
Description Q3 ,
The IRS2004 is a high voltage, high speed power JJJ/
MOSFET and IGBT driver with dependent high- and low-
side referenced output channels. Proprietary HVIC and
latch immune CMOS technologies enable ruggedized
monolithic construction. The logic input is compatible
with standard CMOS or LSTTL output, down to 3.3 V
logic. The output drivers feature a high pulse current buffer stage designed for minimum driver cross-
conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in the high-side
configuration which operates from 10 V to 200 V.
8 Lead SOIC 8 Lead PDIP
IRS2004S IRS2004
Typical Connection
up to 200 V
(Refer to Lead Assignment for correct pin configuration). This diagram shows electrical
connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
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International IRS2004(S) PbF
152R Rectifier
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are
measured under board mounted and still air conditions.
Symbol Definition Min. Max. Units
VB High-side floating absolute voltage -0.3 225
Vs High-side floating supply offset voltage VB - 25 VB + 0.3
VH0 High-side floating output voltage Vs - 0.3 VB + 0.3
VCC Low-side and logic fixed supply voltage -0.3 25 V
VLO Low-side output voltage -0.3 Vcc + 0.3
VIN Logic input voltage (IN & S70) -0.3 Vcc + 0.3
st/dt Allowable offset supply voltage transient - 50 V/ns
Pb Package power dissipation @ TA s +25 "C (8 lead PDIP) - 1.0 w
(8 lead SOIC) - 0.625
. . . . (8 lead PDIP) - 125
RthJA Thermal resistance, junction to ambient °CNV
(8 lead SOIC) - 200
TJ Junction temperature - 150
Ts Storage temperature -55 150 ''C
TL Lead temperature (soldering, 10 seconds) - 300
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. The Vs offset rating is tested with all supplies biased at a 15 V differential.
Symbol Definition Min. Max. Units
VB High-side floating supply absolute voltage Vs + 10 Vs + 20
Vs High-side floating supply offset voltage Note 2 200
VH0 High-side floating output voltage Vs VB V
Vcc Low-side and logic Fixed supply voltage 10 20
VLo Low-side output voltage 0 Vcc
VIN Logic input voltage (IN & S70) 0 Vcc
TA Ambient temperature -40 125 ''C
Note I: Logic operational for Vs of -5 V to +200 V. Logic state held for Vs of -5 V to -VBs. (Please refer to the Design Tip
DT97-3 for more details).
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