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IRS2001-IRS2001PBF-IRS2001SPBF
High and Low Side Driver
Data Sheet No. PD60268 revA
International
ISER Rectifier IRS2001(S)PbF
HIGH AND LOW SIDE DRIVER
Features Product Summary
q Floating channel designed for bootstrap operation
q Fully operational to +200 V VOFFSET 200 V max.
q Tolerant to negative transient voltage, dV/dt immune
q Gate drive supply range from 10 V to 20 V ko l 200 mA/42O mA
q Undervoltage lockout VOUT 10 V - 20 V
O 3.3 V, 5 V, and 15 V logic input compatible
q Matched propagation delay for both channels ton/off (typ.) 160 ns/150 ns
0 Outputs in phase with inputs
. RoHS compliant Delay Matching 50 ns
Description
The IRS2001 is a high voltage, high speed power Packages
MOSFET and IGBT driver with independent high-side
and Iow-side referenced output channels. Proprietary
HVIC and latch immune CMOS technologies enable
ruggedized monolithic construction. The logic input J _
is compatible with standard CMOS or LSTTL output, ‘J
down to 3.3 V logic. The output drivers feature a high
pulse current buffer stage designed for minimum driver ''eiif2of 8-Lead PDIP
cross-conduction. The Mating channel can be used to IRS2001
drive an N-channel power MOSFET or IGBT in the high-
side conhguration which operates up to 200 V.
Typical Connection
up to 200 V
IRS2001
(Refer to Lead Assignments for correct pin configuration). This diagram shows electrical connections only.
Please refer to our Application Notes and DesignTips for proper circuit board layout.
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International IRS2001(S)PbF
IEER Rectifier
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
Symbol Definition Min. Max. Units
VB High-side floating supply voltage -0.3 225
Vs High-side floating supply offset voltage VB - 25 VB + 0.3
VH0 High-side floating output voltage Vs - 0.3 Vs + 0.3 V
Vcc Low-side and logic fixed supply voltage -0.3 25
VLO Low-side output voltage -O.3 VCC + 0.3
VIN Logic input voltage (HIN & LIN) -0.3 VCC + 0.3
dl/s/dt Allowable offset supply voltage transient - 50 V/ns
PD Package power dissipation @ TA 5 +25 °C (8 lead PDIP) - 1.0 W
(8 lead SOIC) - 0.625
. . . . (8 lead PDIP) - 125
RthJA Thermal resistance, junction to ambient °C/W
(8 lead SOIC) - 200
TJ Junction temperature - 150
Ts Storage temperature -55 150 t
TL Lead temperature (soldering, 10 seconds) - 300
Recommended Operating Conditions
The input/output logic timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. The Vs offset rating is tested with all supplies biased at a 15 V differential.
Symbol Definition Min. Max. Units
VB High-side floating supply absolute voltage Vs + 10 Vs + 20
Vs High-side floating supply offset voltage Note 1 200
VH0 High-side floating output voltage Vs VB V
Vcc Low-side and logic Foted supply voltage 10 20
l/LO Low-side output voltage 0 Vcc
VIN Logic input voltage (HIN & LIN) 0 Vcc
TA Ambient temperature -40 125 °C
Note 1: Logic operational for Vs of -5 V to +200 V. Logic state held tor Vs of -5 V to -VBs. (Please refer to the Design
Tip DT97-3 tor more details).
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