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IR3094M-IR3094MPBF-IR3094MTRPBF
A full featured, cost effective, single chip solution to offers a compact, efficient solution for high current POL converters.
International
. . Data Sheet No. PD 94716
19R Rectifier
IR3094PBF
3 PHASE PWM CONTROLLER FOR POINT OF LOAD
DESCRIPTION
The IR3094 Control IC provides a full featured, cost effective, single chip solution to offers a compact,
efficient solution for high current POL converters. Control and 3 Phase Gate Drive functions are integrated
into a single space-saving IC.
FEATURES
0.85V Reference Voltage
3A GATELX Pull Down Drive Capability
Programmable 100KHz to 540KHz oscillator
Programmable Voltage Positioning (can be disabled)
Programmable Softstart
Programmable Hiccup Over-Current Protection with Delay to prevent false triggering
Simplified Powergood provides indication of proper operation and avoids false triggering
Operates up to 16V converter input with 7.5V Under-Voltage Lockout
4.36V Under-Voltage Lockout threshold for gate driver voltage
Adjustable Voltage, 150mA Bias Regulator provides MOSFET Drive Voltage
Enable Input
OVP Flag Output detects high side fet short at powerup
Separate OVP sense line to sense the output voltage and latched OVP with protection
Inductor DCR sensing for current sensing will support up to 5.1 V output applications
Available 48L MLPQ package
ORDERING INFORMATION
Device Order Quantity
IR3094MTRPBF 3000 per Reel
IR3094MPBF 100 piece strips
PACKAGE INFORMATION
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- NC "'ti5 88PGND1 - 48L MLPQ
- ROSC GATEL1 -
- VOSNS- IR3094 VCCL1_2 - (7 X 7 mm Body)
_ OCSET 5VUVL - - 27OC/W
_ VREF 4&DMLPQ GATEL2 - JA -
- VDRP PGND2 - e
- FB GATEH2 -
- EAOUT VCCH2 -
- SS/DEL VCCH3 -
- SCOMP2 GATEH3 -
- SCOMP3 PGND3 -
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Page 1 of 29 09/26/05
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International
19R Rectifier
IR3094PBF
PIN DESCRIPTION
PIN# PIN SYMBOL PIN DESCRIPTION
1 NC Not connected
2 NC Not connected
3 ROSC Connect a resistor to VOSNS- to program oscillator frequency, OCSET and STBIAS bias currents.
4 VOSNS- Remote Sense Input. Connect to ground at the load.
5 OCSET Programs thehiccup oVTcurfent threshold through an external resistor tied to VREF and an internal current
source. The bias current IS a function of ROSC.
6 VREF 0.85V Reference voltege. Current Sensing and Over Current Protection are referenced to this pin. An
external RC network tied to VOSNS- IS needed for the compensation.
7 VDRP Buffered average current information. Connect an external resistor to FB to program converter output.
8 FB Inverting input to the Error Amplifier.
9 EAOUT Output of the Error Amplifier.
10 SS/DEL Controls Converter Softstart, Power Good, and Over-Current Timing. Connect an external capacitor to
LGND to program the tImIng.
11 SCOMP2 Compensation for the Current Share control loop. Connect a capacitor to ground to set the control loop’s
bandwidth. Phase 2 IS forced to match phase I's current.
12 SCOMP3 Compensation for the Current Share control loop. Connect a capacitor to ground to set the control loop’s
bandwidth. Phase 3 IS forced to match phase I's current.
13 LGND Local Ground and IC substrate connection.
14 SETBIAS External resistor to ground sets voltage at BIASOUT pin. Bias current is a function of ROSC.
15 VCC Power for internal circuitry and source for BIASOUT regulator.
16 CSINP3 Non-inverting input to the Phase 3 Current Sense Amplifier.
17 CSINM3 Inverting input to the Phase 3 Current Sense Amplifier.
18 BIASOUT 150mA open-looped regulated voltage set by SETBIAS for GATE drive bias.
19 PWRGD Open Collector output that drives low during Softstart or any fault condition. Connect external pull-up.
20 CSINP2 Non-inverting input to the Phase 2 Current Sense Amplifier.
21 CSINM2 Inverting input to the Phase 2 Current Sense Amplifier.
22 NC Not connected
23 VCCL3 Power for Phase 3 Low-Side Gate Driver.
24 GATEL3 Phase 3 Low-Side Gate Driver Output and input to GATEH3 non-overlap comparator.
25 PGND3 Return for Phase 3 Gate Drivers.
26 GATEH3 Phase 3 High-Side Gate Driver Output and input to GATELS non-overlap comparator.
27 VCCH3 Power for Phase 3 High-Side Gate Driver.
28 VCCH2 Power for Phase 2 High-Side Gate Driver.
29 GATEH2 Phase 2 High-Side Gate Driver Output and input to GATEL2 non-overlap comparator.
30 PGND2 Return for Phase 2 Gate Drivers.
31 GATEL2 Phase 2 Low-Side Gate Driver Output and input to GATEH2 non-overlap comparator.
32 5VUVL Can be used_t_o monitor the driver supply voltage or 5V supply voltage when converting from 5V. An under
voltage condition initiates Soft Start.
33 VCCLC2 Power for Phase 1 and 2 Low-Side Gate Drivers.
34 GATEL1 Phase 1 Low-Side Gate Driver Output and input to GATEH1 non-overlap comparator.
35 PGND1 Return for Phase 1 Gate Drivers.
36 GATEH1 Phase 1 High-Side Gate Driver Output and input to GATEL1 non-overlap comparator.
37 VCCH1 Power for Phase 1 High-Side Gate Driver.
38 NC Not connected
39 CSINM1 Inverting input to the Phase 1 Current Sense Amplifier.
40 CSINP1 Non-inverting input to the Current Sense Amplifier.
41 OVP Output that drives high during an Over-Voltage condition.
42 ENABLE Enable Input. A logic low applied to this pin puts the IC into Fault mode.
43 OVPSNS Dedicated output voltage sense pin for Over Voltage Protection.
44 5VREF Decoupling for internal voltage reference rail.
45 NC Not connected
46 NC Not connected
47 NC Not connected
48 NC Not connected
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