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IR21362STRPBF-IR2136STRPBF
3 Phase Driver, Soft Turn-on, Non-inverting Input Separate High and Low Side Inputs, 200ns Deadtime.
International IR213(6,62,63,65,66,67,68)(J&S) & PbF
TOR Rectifier
Data Sheet No. PD60166 revU
Internoiiqhol IR2136llR21362llR21363/lR21365/
TOR Rectifier lR21366/lR21367/lR21368 (J&S) & (PbF)
3-PHASE BRIDGE DRIVER
Features Packages
q Floating channel designed for bootstrap operation
q Fully operational to +600 V
o Tolerant to negative transient voltage, dV/dt immune
q Gate drive supply range from 10 V to 20 V (IR2136/
IR21368), 11.5 v to 20 v (IR21362D), or 12 v to 20 v
(lR21363/lR21365/lR21366/IR21367) 28-Lead SOIC 28-Lead PDIP
o Undervoltage lockout for all channels
q Over-current shutdown turns off all six drivers
q Independent 3 half-bridge drivers ',
o Matched propagation delay for all channels 113'
o Cross-conduction prevention logic
q Low side output out of phase with inputs. High side outputs 44-Lead PLCC mo 12 Leads
out of phase (IR213(6,63, 65, 66, 67, 68)), or in phase
(IR21362) with inputs
q 3.3 V logic compatible
q Lower di/dt gate drive for better noise immunity
q Externally programmable delay for automatic fault clear
. All parts are LEAD-FREE
. . Feature Comparison: IR213(6,62,63,65,66,67,68)
Description
The IR2136x (J&S) are high voltage, high Part IR2136 IR21362 IRZ1363 IR21365 IR21366 IR21367 IR21368
speed Te" MOSFET and IGBT drivers wit.h. InputLugic mm mum mm mm mm W.W mm
three independent high and low side Ton (lyp.) 400 ns 400 ns 400 ns 400 ns 250 ns 250 ns 400 ns
refe.r.en.c.ed output . channels for 3-phase Tom,” 380ns 380 ns 380 ns 380 ns 180 ns 180 ns 380 ns
applications. Proprietary HVIC technology vmitYp.) 2.7V 2.7V 2.7V 2.7V 2.0V 2.0V 2.0V
enables ruggedized monolithic construction. v.1 (typ.) 1.7V 1.7V 1.7V 1.7V 1.3V 1.3V 1.3V
Logic inputs are compatible with CMOS or Ugggy (’54:; bl')) 314% 14132: 314% 1413;; 1i'/f,
LSTTL outputs, down to 3.3 V logic. A current UVCC/BS- Gi, 94V ia) 11:0V ia) 11:0V G(,
trip function which terminates all six outputs
can be derived from an external current sense resistor. An enable function is available to terminate all six outputs simultaneously. An
open-drain FAULT signal is provided to indicate that an overcurrent or Undervoltage shutdown has occurred. Overcurrent fault
conditions are cleared automatically after a delay programmed externally via an RC network connected to the RCIN input. The output
drivers feature a high pulse current buffer stage designed for minimum driver cross-conduction. Propagation delays are matched to
simplify use in high frequency applications. The floating channels can be used to drive N-channel power MOSFETs or IGBTs in the
high side configuration which operates up to 600 V.
. . _I
Typical Connection 7,
Up t1600 V
Vcc C) Vcc
HlN 1,2,3/HIN 1,2,3 o- HiN 1,2,3/H1N 1,23 Vn 1.2.! A ("iiji"
LIN1.2,3 C) LIN 1.23 11012.3 FF
FAULT -
FAULT CY Vsus "T"
EN 0 EN
(R f t L d _ C. TO
e er 0 ea
Assignments for correct :: LOAD
pin configuration).This I--- RCIN It) 0
diagram shows electrical - ITRIP LO 1,2,3 l"
connections only. Please Vss COM
refer to our Application
Notes and Design Tips for
proper circuit board IR213(6,62,63,65,66,67,68)
layout.
GND C) v v
www.i_rf.com 1
International IR213(6,62,63,65,66,67,68)(J&S) & PbF
TOR Rectifier
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage
parameters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are
measured under board mounted and still air conditions.
Symbol Definition Min Max Units
Vs High side offset voltage VB1,2,3' 25 V3123 + 0.3
VB High side floating supply voltage -0.3 625
VH0 High side floating output voltage Vsms- 0.3 V3123 + 0.3
Vcc Low side and logic fixed supply voltage -0.3 25
Vss Logic ground Vcc - 25 Vcc + 0.3 V
VLo1,2,3 Low side output voltage -O.3 Vcc + 0.3
Lower of
V.N Input voltage LIN, HIN, ITRIP, EN I/ss -0.3 (Vss + 15) or
Vcc + 0.3)
VRCIN RCIN input voltage Vss -0.3 Vcc + 0.3
vFLT FAULT output voltage Vss -0.3 Vcc + 0.3
dV/dt Allowable offset voltage slew rate - 50 V/ns
(28 lead PDIP) - 1.5
Package power dissipation
PD @ TA s +25 "C (28 lead SOIC) - 1.6 W
(44 lead PLCC) - 2.0
(28 lead PDIP) - 83
Thermal resistance, junction to o
RthJA ambient (28 lead SOIC) - 78 C/W
(44 lead PLCC) - 63
To Junction temperature - 150
Ts Storage temperature -55 150 “C
TL Lead temperature (soldering, 10 seconds) - 300
Recommended Operating Conditions
The input/output logic-timing diagram is shown in Fig. 1. For proper operation the device should be used within the
recommended conditions. All voltage parameters are absolute referenced to COM. The Vs offset ratings are tested
with all supplies biased at a 15 V differential.
Symbol Definition Min Max Units
IR213(6,68) Vs1,2,3 +10 Vs1,2,3 + 20
V3123 High side floating supply voltage IR21362 V5123 +11.5 V3123 + 20
IR213(6,63,65,66,67) V3123 +12 V3123 + 20
Vs1,2,3 High side floating supply offset voltage Note 1 600
VHo1,2,3 High side output voltage V3123 V3123
I/cola:, Low side output voltage 0 Vcc V
. . IR213(6,68) 10 20
Vcc \ngligglge and logic fixed supply IR21362 11.5 20
IR213(6,63,65,66,67) 12 20
l/ss Logic ground -5 5
vFLT FAULT output voltage Vss Vcc
VRC'N RCIN input voltage Vss Vcc
Note 1: Logic operational for Vs of (COM - 5 V) to (COM + 600 V). Logic state held for Vs of (COM - 5 V) to (COM - V35).
(Please refer to the Design Tip DT97-3 for more details).
Note 2: All input pins and the ITRIP and EN pins are internally clamped with a 5.2 V zener diode.
2
