IR2132JPBF ,3 Phase Driver, Inverting Input, 0.8us Deadtime in a mod. 44-lead PLCC packageData Sheet No. PD60019 Rev.PIR2130/IR2132(J)(S) & (PbF)3-PHASE BRIDGE DRIVERProduct Summary
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IR2130-IR2130J-IR2130JPBF-IR2130JTR-IR2130PBF-IR2130S-IR2132-IR2132J-IR2132JPBF-IR2132JTR-IR2132PBF-IR2132S-IR2132S.-IR2132SPBF-IR2132STR
3 Phase Driver, Inverting Input, 2.5us Deadtime in a 28-pin DIP package
Data Sheet No. PD60019 Rev.P
International
TOR Rectifier lR2130/IR2132(J)(S) & (PbF)
3-PHASE BRIDGE DRIVER
Features Product Summary
q 1tf'Jgr)t'ir2t/ttsell1dv" bootstrap operation VOFFSET 600V max.
Jeirtai1t,ou1e,9ative transient voltage Ityrl- 200 mA I 420 mA
I (jreir11rtt';'7cia7t1rir2"tlh1lnt/..oel01/ . VOUT IO - 20V
IEEZEZLAL’ZEE itiufei)Cet1rr'il','e'rf all SIX drivers ttm/oft am 675 & 425 ns
q Matched propagation delay for all channels
q 2.5Vlogic compatible Deadtime (typ.) 2.5 us (IR2130)
q Outputs out ofphase with inputs 0.8 ps (IR2132)
q Cross-conduction prevention logic
q Also available LEAD-FREE
Description
Packages
The IR2130/lR2132(J)(S) is a high voltage, high speed ''iiity
power MOSFET and IGBT driver with three indepen- sCfiiti'i'i'
dent high and low side referenced output channels. Pro- . B'sl
prietary HVIC technology enables ruggedized 28-Lead SOIC
monolithic construction. Logic inputs are compatible with
CMOS or LSTTL outputs, down to 2.5V logic. A
ground-referenced operational amplifier provides
analog feedback of bridge current via an external cur-
rent sense resistor. A current trip function which termi-
nates all six outputs is also derived from this resistor.
An open drain FAULT signal indicates if an over-cur-
rent or undervoltage shutdown has occurred. The output drivers feature a high pulse current bufferstage designed
for minimum drivercross-conduction. Propagation delays are matched to simplify use at high frequencies. The
floating channels can be used to drive N-channel power MOSFETs or IGBTs in the high side configuration
which operate up to 600 volts.
Typical Connection upto600V
H|N1.2.3
FAt-JLT
HINI,2,3 H0123
m V5123
FAt-JLT
- --o LOAD
(Refer to Lead Assignments for correct pin configuration). This/These diagram(s) show electrical connections only. Please refer
to our Application Notes and DesignTips for proper circuit board layout.
1
International
TOR Rectifier
IR2'130/lR2132(J)(S) &(PbF)
Absolute Maximum Ratings
Absolute Maximum Ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to V50. The Thermal Resistance and Power Dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in Figures 50 through 53.
Symbol Definition Min. ng. Units
V31 2 3 High Side Floating Supply Voltage -0.3 625
V31 2 3 High Side Floating Offset Voltage V31 2 3 - 25 V31 2 3 + 0.3
VH01,2,3 High Side Floating Output Voltage V312 3 - 0.3 V312 3 + 0.3
Vcc Low Side and Logic Fixed Supply Voltage -O.3 25
Vss Logic Ground Vcc - 25 Vcc + 0.3
VLo1,2,3 tow Side Output Voltage -0.3 Vcc + 0.3
VIN Logic Input Voltage (HIN1,2,3, LIN1,2,3 & ITRIP) Vss - 02 Nss + 15) or V
(Vcc + O.3)
whichever is
VFLT FAULT OutputVoItage VSS - 0.3 Vcc + 0.3
VCAO Operational Amplifier Output Voltage Vss - 0.3 Vcc + 0.3
VCA- Operational Amplifier Inverting InputVoltage Vss - 0.3 Vcc + 0.3
dVs/dt Allowable Offset Supply Voltage Transient - 50 V/ns
PD Package Power Dissipation @ TAS: +25°C (28 Lead DIP) - 1.5
(28 Lead SOIC) - 1.6 W
(44 Lead PLCC) - 2.0
RthJA Thermal Resistance, Junction to Ambient (28 Lead DIP) - 83
(28 Lead SOIC) - 78 ''CNV
(44 Lead PLCC) - 63
T J Junction Temperature - 150
Ts Storage Temperature -55 150 ''C
TL Lead Temperature (Soldering, 10 seconds) - 300
Recommended Operating Conditions
The Input/Output logic timing diagram is shown in Figure 1. For proper operation the device should be used within the
recommended conditions. All voltage parameters are absolute voltages referenced to V30. The vs offset rating is tested
with all supplies biased at 15V differential. Typical ratings at other bias conditions are shown in Figure 54.
Symbol Definition Min. Max. Units
V51 2 3 High Side Floating Supply Voltage V51 2 3 + 10 V31 2 3 + 20
V3123 High Side Floating Offset Voltage Note 1 600
VH01 2 3 High Side Floating Output Voltage V31 2 3 V31 2 3
Vcc Low Side and Logic Fixed Supply Voltage 10 20
l/ss Logic Ground -5 5
VLo1,2,3 Low Side Output Voltage 0 Vcc
vm Logic Input Voltage (W23. LIN1,2,3 & ITRIP) vss Vss + 5 V
VFLT WT Output Voltage Vss Vcc
VCAO Operational AmplferOutputVoltage Vss Vss + 5
VcA. Operational Amplifier Inverting InputVoltage Vss Vss + 5
TA Ambient Temperature -40 125 ''C
Note I: Logic operational for Vs of (Vso - 5V) to (V30 + 600V). Logic state held for Vs of Nso - 5V) to Nso - V33).
(Please refer to the Design Tip DT97-3 for more details).
Note 2: All input pins, C - and CAO pins are internally clamped with a 5.2V zener diode.
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