IR2113-1PBF ,HIGH AND LOW SIDE DRIVERapplications. Thefloating channel can be used to drive an N-channel power MOSFET or IGBT in the hi ..
IR2113-2 ,High and Low Side Driver, All High Voltage Pins On One Side, Separate Logic and Power Ground, Shut-Down, High Creepage Package in a 16-pin DIP -2 leads packageFeaturesProduct Summary• Floating channel designed for bootstrap operation V (IR2110) 500V max.OF ..
IR2113-2PBF ,HIGH AND LOW SIDE DRIVERFeaturesProduct Summary• Floating channel designed for bootstrap operation V (IR2110) 500V max.OF ..
IR2113PBF ,High and Low Side Driver, All High Voltage Pins On One Side, Separate Logic and Power Ground, Shut-Down in a 14-pin DIP packageelectrical characteristics are measured using the test circuit shown in Figure 3.Symbol Definition ..
IR2113S ,High and Low Side Driver, All High Voltage Pins On One Side, Separate Logic and Power Ground, Shut-Down in a 16-lead SOIC packageFeaturesProduct Summary• Floating channel designed for bootstrap operation V (IR2110) 500V max.OF ..
IR2113S. ,High and Low Side Driver, All High Voltage Pins On One Side, Separate Logic and Power Ground, Shut-Down in a 16-lead SOIC packageElectrical CharacteristicsV (V , V , V ) = 15V, C = 1000 pF, T = 25°C and V = COM unless otherwise ..
IRSF3021L ,Intelligent Power Switch 1 Channel Low Side Driver in a SOT-223 Package
IRSF3021L ,Intelligent Power Switch 1 Channel Low Side Driver in a SOT-223 Package
IRSF3031 ,Intelligent Power Switch 1 Channel Low Side Driver in a TO-220AB PackageFeaturesProduct Summary• Controlled slew rate reduces EMI• Over temperature protectionV 50 Vds(clam ..
IRSF3031L ,Intelligent Power Switch 1 Channel Low Side Driver in a SOT-223 PackageBlock DiagramDrainDRAINBias & RefInput +INPUT3.5V-+S Q1V-R Q+-Vref-+ TjGroundIsolationSourceSOURCE ..
IRSF3031LTR ,Intelligent Power Switch 1 Channel Low Side Driver in a SOT-223 PackageApplicationsMOSFET with built-in short circuit, over-temperature, ESD and• Solenoid Driverover-volt ..
IRSF3031LTR ,Intelligent Power Switch 1 Channel Low Side Driver in a SOT-223 PackageData Sheet No. PD 60069-HIRSF3031 (NOTE: For new designs, werecommend IR’s new products IPS021 and ..
IR2113-1PBF-IR2113-2PBF
HIGH AND LOW SIDE DRIVER
Data Sheet No. PD60147 rev.U
International
TOR Rectifier IR2110(-'1-2)(S)PbFllR2113(-1-2)(S)PbF
HIGH AND LOW SIDE DRIVER
Features Product Summary
. Floating channel designed for bootstrap operation
Fully operational to +500V or +600V VOFFSET (IR2110) 500V max.
Tolerant to negative transient voltage (IR21 13) 600V max.
dV/dt immune
. Gate drive supply range from 10 to 20V kyrl- 2A / 2A
. Undervoltage lockout for both channels
. 3.3V logic compatible VOUT 10 - 20V
Separate logic supply range from 3.3V to 20V
Logic and power ground ehN offset ton/off (typ.) 120 & 94 ns
. CMOS Schmitt-triggered inputs with pull-down .
. C . . Delay Matching (IR2110) 10 ns max.
ycle by cycle edge-trlggered shutdown logic IR21 13 20
. Matched propagation delay for both channels ( ) ns max.
. Outputs in phase with inputs Packages
Description
The lR2110/lR2113 are high voltage, high speed power MOSFET and
IGBT drivers with independent high and low side referenced output chan-
nels. Proprietary HVIC and latch immune CMOS technologies enable
ruggedized monolithic construction. Logic inputs are compatible with
standard CMOS or LSTTL output, down to 3.3V logic. The output
drivers feature a high pulse current buffer stage designed for minimum
driver cross-conduction. Propagation delays are matched to simplify use in high frequency applications. The
floating channel can be used to drive an N-channel power MOSFET or IGBT in the high side configuration which
operates up to 500 or 600 volts.
16-Lead SOIC
14-Lead PDIP IR2110S/lR2113S
lR2110/lR2113
Typical Connection up to 500V or 600V
(Refer to Lead Assignments for correct pin coMguration). This/These diagram(s) show electrical
connections only. Please refer to our Application Notes and DesignTips for proper circuit board layout.
1
International
IR21'10(-1-2)(S)PbFllR2113(-1-2)(S)PbF mRecmer
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions. Additional information is shown in Figures 28 through 35.
Symbol Definition Min. Max. Units
VB High side floating supply voltage (IR2110) -O.3 525
(IR2113) -0.3 625
vs High side floating supply offset voltage VB - 25 VB + 0.3
VH0 High side floating output voltage Vs - 0.3 VB + 0.3
Vcc Low side fixed supply voltage -0.3 25
VLo Low side output voltage -0.3 VCC + 0.3 V
VDD Logic supply voltage -0.3 1/ss + 25
I/ss Logic supply offset voltage VCC - 25 V00 + 0.3
VIN Logic input voltage (HIN, LIN & SD) Vss - 0.3 VDD + 0.3
st/dt Allowable offset supply voltage transient (figure 2) - 50 V/ns
PD Package power dissipation @ TA 3 +25°C (14 lead DIP) - 1.6 W
(16 lead SOIC) - 1.25
RTHJA Thermal resistance, junction to ambient (14 lead DIP) - 75 o
(16 lead SOIC) - 100 C/W
TJ Junction temperature - 150
Ts Storage temperature -55 150 "C
TL Lead temperature (soldering, 10 seconds) - 300
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The vs and Vss offset ratings are tested with all supplies biased at 15V differential. Typical
ratings at other bias conditions are shown in figures 36 and 37.
Symbol Definition Min. Max. Units
VB High side floating supply absolute voltage Vs + 10 Vs + 20
Vs High side floating supply offset voltage (IR2110) Note 1 500
(IR2113) Note 1 600
VH0 High side floating output voltage vs VB
Vcc Low side Fixed supply voltage 10 20 V
VLo Low side output voltage 0 VCC
VDD Logic supply voltage I/ss + 3 Vss + 20
N/ss Logic supply offset voltage -5 (Note 2) 5
VIN Logic input voltage (HIN, LIN & SD) l/ss VDD
TA Ambient temperature -40 125 ''C
Note 1: Logic operational for Vs of -4 to +500V. Logic state held for Vs of -4V to NBS. (Please refer to the Design Tip
DT97-3 for more details).
Note 2: When VDD < 5V, the minimum l/ss offset is limited to A/DD.
