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IR2105-IR2105S
Half Bridge Driver, Single Input, All High Voltage Pins On one Side, Fixed 520ns Deadtime in a 8-pin DIP package
International
TCdl Rectifier
Data Sheet No. PD60139J
IIRZ1|05
Features
q Floating channel designed for bootstrap operation
Fully operational to +600V
Tolerant to negative transient voltage
dV/dt immune
q Gate drive supply range from 10 to 20V
q Undervoltage lockout
q 5V Schmitt-triggered input logic
q Cross-conduction prevention logic
q Internally set deadtime
. High side output in phase with input
. Match propagation delay for both channels
Description
The IR2105 is a high voltage, high speed power
MOSFET and IGBT driver with dependent high and
low side referenced output channels. Proprietary
HVIC and latch immune CMOS technologies en-
able ruggedized monolithic construction. The logic
input is compatible with standard CMOS or LSTTL
outputs. The output drivers feature a high pulse
current buffer stage designed for minimum driver
cross-conduction. The floating channel can be used
to drive an N-channel power MOSFET or IGBT in
HALF BRIDGE DRIVER
Product Summary
VOFFSET 600V max.
lo+l- 130 mA I 270 mA
Vow IO - 20V
tonmn(typ.) 680 & 150 ns
Deadtime (typ.) 520 ns
Packages
8 Lead PDIP
the high side configuration which operates from 10 8 Lead SOIC
to 600 volts.
Typical Connection
up to 600V
IR2105
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
International
TOR Rectifier
Symbol Definition Min. Max. Units
VB High side floating absolute voltage -O.3 625
Vs High side floating supply offset voltage VB - 25 VB + 0.3
VH0 High side floating output voltage Vs - 0.3 VB + 0.3
Vcc Low side and logic fixed supply voltage -O.3 25 V
VLO Low side output voltage -0.3 Vcc + 0.3
VIN Logic input voltage -0.3 VCC + 0.3
st/dt Allowable offset supply voltage transient - 50 V/ns
PD Package power dissipation @ TA LC +25°C (8 Lead DIP) - 1.0
(8 Lead SOIC) - 0.625 W
RthJA Thermal resistance, junction to ambient (8 Lead DIP) - 125 ''CA/V
(8 Lead SOIC) - 200
T J Junction temperature - 150
Ts Storage temperature -55 150 ''C
TL Lead temperature (soldering, 10 seconds) - 300
Recommended Operating Conditions
The input/output logic timing diagram is shown in hgure I. For proper operation the device should be used within the
recommended conditions. The Vs offset rating is tested with all supplies biased at 15V differential.
Symbol Definition Min. Max. Units
VB High side floating supply absolute voltage Vs + 10 Vs + 20
Vs High side floating supply offset voltage Note 1 600
VH0 High side floating output voltage Vs V53
Vcc Low side and logic med supply voltage 10 20 V
VLo Low side output voltage 0 VCC
VIN Logic input voltage 0 Vcc
TA Ambient temperature -40 125 "C
Note I: Logic operational for Vs of -5 to +600\/. Logic state held for Vs of -5V to A/BS.
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