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IRS2130DJ ,3 Phase Driver, Inverting Input, 2.5us Deadtime in a mod. 44-lead PLCC package PRELIMINARY Data Sheet No. PD60256 revA ..
IRS2130DPBF ,3 Phase Driver, Inverting Input, 2.5us Deadtime in a 28-pin DIP package PRELIMINARY Data Sheet No. PD60256 revA ..
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IR2101STRPBF
High and Low Side Driver, Noninverting Inputs
Data Sheet No. PD60043 Rev.0
International
ISBR Rectifier IR2101(S)/lR2102(S)&(PbF)
HIGH AND LOW SIDE DRIVER
Features Product Summary
q Floating channel designed for bootstrap operation
Fully operational to +600V VOFFSET 600V max.
Tolerant to negative transient voltage + -
dV/dt immune Io / 130 mA / 270 mA
q Gate drive supply range from 10 to 20V VOUT IO - 20V
q Undervoltage lockout
q 3.3V, 5V, and 15V logic input compatible ton/off (typ.) 160 8 150 ns
0 Matched propagation delay for both channels
q Outputs in phase with inputs (IR2101) or out of Delay Matching 50 ns
phase with inputs (IR2102)
q Also available LEAD-FREE Packages
Description
The lR2101(S)/lR2102(S) are high voltage, high speed
power MOSFET and IGBT drivers with independent
high and low side referenced output channels. Pro-
prietary HVIC and latch immune CMOS technologies 8-Lead SOIC 8-Lead PDIP
enable ruggedized monolithic construction. The logic 1R2101S/IR2102S IR2101/lR2102
input is compatible with standard CMOS or LSTTL
output, down to 3.3V logic. The output drivers feature a high pulse current buffer stage designed for minimum
driver cross-conduction. The floating channel can be used to drive an N-channel power MOSFET or IGBT in
the high side configuration which operates up to 600 volts.
Typical Connection
up in 600V
IR2101
LIN TO
up to 600V
(Refer to Lead Assignments for correct pin L(Tngu
conrguration). This/These diagram(s) show
electrical connections only. Please refer to
our Application Notes and DesignTips for
proper circuit board layout.
IR2102
1
|R2101(S)/IR2102(S) & (PbF)
Absolute Maximum Ratings
Absolute maximum ratings indicate sustained limits beyond which damage to the device may occur. All voltage param-
eters are absolute voltages referenced to COM. The thermal resistance and power dissipation ratings are measured
under board mounted and still air conditions.
International
TOR Rectifier
Symbol Definition Min. Max. Units
VB High side floating supply voltage -O.3 625
Vs High side floating supply offset voltage VB - 25 VB + 0.3
VH0 High side floating output voltage Vs - 0.3 VB + 0.3 V
Vcc Low side and logic fixed supply voltage -0.3 25
Wo Low side output voltage -0.3 VCC + 0.3
VIN Logic input voltage (HIN & LIN) -0.3 VCC + 0.3
dVs/dt Allowable offset supply voltage transient - 50 V/ns
PD Package power dissipation @ TA S +25°C (8 lead PDIP) - 1.0
(8 lead SOIC) - 0.625 W
RthJA Thermal resistance, junction to ambient (8 lead PDIP) - 125 °CNV
(8 lead SOIC) - 200
Tu Junction temperature - 150
Ts Storage temperature -55 150 ''C
TL Lead temperature (soldering, 10 seconds) - 300
Recommended Operating Conditions
The input/output logic timing diagram is shown in figure 1. For proper operation the device should be used within the
recommended conditions. The Vs offset rating is tested with all supplies biased at 15V differential.
Symbol Definition Min. Max. Units
VB High side floating supply absolute voltage Vs + 10 Vs + 20
Vs High side floating supply offset voltage Note 1 600
VH0 High side floating output voltage Vs VB V
VCC Low side and logic foted supply voltage 10 20
VLo Low side output voltage 0 Vcc
VIN Logic input voltage (HIN & LIN) (IR2101) & (WI am) (IR2102) 0 Vcc
TA Ambient temperature -40 125 °C
Note 1: Logic operational for Vs of -5 to +600V. Logic state held for Vs of -5V to NBS. (Please refer to the Design Tip
DT97-3 for more details).
