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IPF05N03LA
OptiMOS®2
. |PD05N03LA IPF05N03LA
Infineon
tec h n o l og i es IPS05N03LA IPU05N03LA
optiMOsf2 Power-Transistor
Product Summary
Features Vos 25 V
. Ideal for high-frequency dc/dc converters RDS(on),max (SMD version) 5.1 m9.
. Qualified according to JEDECI) for target application
I D 50 A
. N-channel, logic level
. Excellent gate charge x RDswn) product (FOM) SE“;
. Superior thermal resistance gate
. 175 ''C operating temperature
source
Type |PD05N03LA |PF05N03LA FS05N03LA IPU05N03LA
Package P-T0252-3-11 P-T0252-3-23 P-T0251-3-1 1 P-T0251-3-21
Ordering Code Q67042-S4144 Q67042-S4194 Q67042-S4244 Q67042-S4230
Marking 05N03LA 05N03LA 05N03LA 05N03LA
Maximum ratings, at Tj=25 ''C, unless otherwise specified
Parameter Symbol Conditions Value Unit
Continuous drain current In Tc=25 002) 50 A
Tc=100 "C 50
Pulsed drain current ho,ruse Tc=25 oc3) 350
Avalanche energy, single pulse EAS ID=45 A, Rss--25 Q 300 mJ
[0:50 A, VDS=20 V,
Reverse diode dv/dt dv/dt dildt=200 Alps, 6 kV/ps
Tj,max=175 ''C
Gate source voltage'') Vss :20 V
Power dissipation Ptot Tc=25 ''C 94 w
Operating and storage temperature Tj, Tstg -55 ... 175 "C
IEC climatic category; DIN IEC 68-1 55/175/56
Rev. 1.7 page 1 2004-05-19
. IPD05N03LA IPF05N03LA
Infineon
tec h n o l og i es IPS05N03LA IPU05N03LA
Parameter Symbol Conditions Values Unit
min. typ. max.
Thermal characteristics
Thermal resistance, junction - case RM; - - 1.6 K/W
SMD version, device on PCB RNA minimal footprint - - 75
6 cm2 cooling areas) - - 50
Electrical characteristics, at Tj=25 ''C, unless otherwise specified
Static characteristics
Drain-source breakdown voltage V(BRmss VGS=O V, ID=1 mA 25 - - V
Gate threshold voltage VGSith) VDS=VGS, ID=50 pA 1.2 1.6 2
z t It d . t I Vrss=25 V, Ves=0 V, o 1 1 A
ero ga e vo age rain curren DSS Tj=25 ''C - . p
VDS=25 V, Vss=0 V,
Tj=125 ''C - 10 100
Gate-source leakage current less VGS=20 V, VDS=O V - 10 100 nA
Drain-source on-state resistance Roswn) VGS=4.5 V, ID=3O A - 6.9 8.6 mn
VGS=4'5 V, ID=3O A,
SMD version - 6.7 8.4
VGS=1O V, ID=3O A - 4.4 5.3
VGS=10 V, ID=3O A,
SMD version - 4.2 5.1
Gate resistance RG - 1 - f2
V >2 l R ,
Transconductance gfs I PSI I DI DS(on)max 31 62 - S
/o=30 A
I) J-STD20 and JESD22
2) Current is limited by bondwire; with aanJc=1.6 K/W the chip is able to carry 106 A.
3) See figure 3
4) Trmax=150 ''C and duty cycle D <0.25 for Vss<-5 v
5) Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 on (one layer, 70 pm thick) copper area for drain
connection. PCB is vertical in still air.
Rev. 1.7
page 2
