IP4770CZ16 ,VGA/video interface with integrated buffers, ESD protection and integrated termination resistors IP4770/71/72CZ16VGA/video interface with integrated buffers, ESD protection and integrated termina ..
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IP4770CZ16-IP4771CZ16-IP4772CZ16
VGA/video interface with integrated buffers, ESD protection and integrated termination resistors
1. General descriptionThe IP4770CZ16, IP4771CZ16, IP4772CZ16 is connected between the VGA/DVI
interface and the video graphics controller and includes level shifting for the DDC signals,
buffering for the SYNC lines as well as high-level ESD protection diodes for the RGB
signal lines.
The level shifting functions are required when the DDC controller operates at a lower
supply voltage than the monitor. T o use this level shifting function the gates of the two
N-channel MOSFET s have to be connected to the supply rail of the DDC transceivers.
Buffering for the SYNC signals is provided by two non-inverting buffers, which accept TTL
input levels and convert these to CMOS compliant output levels between pins VCC(SYNC)
and GND.
The IP4770CZ16 and IP4771CZ16 contain the formerly external termination resistors,
which are typically required for the HSYNC and VSYNC lines of the video interface:
IP4770CZ16: Rsync =55Ω
IP4771CZ16: Rsync =65Ω
IP4772CZ16: Rsync =10 Ω to allow termination of the SYNC lines
All RGB I/Os are protected by a special diode configuration offering a low line capacitance
of 4 pF (maximum) only to provide protection to downstream components for ESD
voltages as high as ±8 kV contact discharge according to IEC 61000-4-2, level4
standard.
2. Features and benefits Integrated high-level ESD protection, buffering, SYNC signal impedance matching and
level shifting Terminal connections with integrated rail-to-rail clamping diodes with downstream ESD
protection of ±8 kV according to IEC 61000-4-2, level 4 standard Backflow protection on DDC lines Drivers for HSYNC and VSYNC lines Bidirectional level shifting N-channel FET s available for DDC clock and DDC data
channels Integrated impedance matching resistors on SYNC lines Line capacitance <4 pF per channel Lead-free package and RoHS compliant
IP4770/71/72CZ16
VGA/video interface with integrated buffers, ESD protection
and integrated termination resistors
Rev. 2 — 19 May 2011 Product data sheet
NXP Semiconductors IP4770/71/72CZ16
VGA/video interface
3. Applications To terminate and to buffer channels, to reduce EMI/RFI and to provide downstream
ESD protection for: VGA interfaces including DDC channels Desktop and notebooks PCs Graphics cards Set-top boxes
4. Ordering information
5. Marking
Table 1. Ordering informationIP4770CZ16 SSOP16 plastic shrink small outline package; 16 leads; body
width 3.9 mm; lead pitch 0.635 mm
SOT519-1
IP4771CZ16
IP4772CZ16
Table 2. Marking codesIP4770CZ16 4770
IP4771CZ16 4771
IP4772CZ16 4772
NXP Semiconductors IP4770/71/72CZ16
VGA/video interface
6. Functional diagramNXP Semiconductors IP4770/71/72CZ16
VGA/video interface
7. Pinning information
7.1 Pinning
7.2 Pin description
Table 3. Pin descriptionVCC(SYNC) 1 supply voltage for SYNC_1 and SYNC_2 level shifter and their connected
ESD protections
VCC(VIDEO) 2 supply voltage for VIDEO_1, VIDEO_2 and VIDEO_3 protection circuits
VIDEO_1 3 video signal ESD protection channel 1
VIDEO_2 4 video signal ESD protection channel 2
VIDEO_3 5 video signal ESD protection channel 3
GND 6 ground
VCC(DDC) 7 supply voltage for DDC_1 and DDC_2 level shifter N-FET gates
BYP 8 this input is used to connect an external 0.2 μF bypass capacitor to increase
ESD withstand voltage rating for the DDC outputs (±8 kV with capacitor or ±4 kV without capacitor)
DDC_OUT1 9 DDC signal output 1; connected to the video connector side of one of the
SYNC lines
DDC_IN1 10 DDC signal input 1; connected to the VGA controller side of one of the SYNC
lines
DDC_IN2 11 DDC signal input 2; connected to the VGA controller side of one of the SYNC
lines
DDC_OUT2 12 DDC signal output 2; connected to the video connector side of one of the
SYNC lines
SYNC_IN1 13 SYNC signal input 1; connected to the VGA controller side of one of the
SYNC lines
SYNC_OUT1 14 SYNC signal output 1; connected to the video connector side of one of the
SYNC lines
SYNC_IN2 15 SYNC signal input 2; connected to the VGA controller side of one of the
SYNC lines
SYNC_OUT2 16 SYNC signal output 2; connected to the video connector side of one of the
SYNC lines
NXP Semiconductors IP4770/71/72CZ16
VGA/video interface
8. Limiting values[1] Pins BYP, VCC(VIDEO) and VCC(SYNC) must be bypassed to ground (pin GND) via a low-impedance ground plane with 0.22 μF, low
inductance, chip ceramic capacitor at each supply pin.
ESD pulse is applied between the pins VIDEO_1, VIDEO_2, VIDEO_3, SYNC_OUT1, SYNC_OUT2, DDC_OUT1, DDC_OUT2 and
GND.
The bypass capacitor at pin BYP can be omitted. In this case the maximum ESD level for DDC_OUT1 and DDC_OUT2 pins is reduced
to ±4kV.
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to ground (GND).
VESD electrostatic discharge voltage IEC 61000-4-2; pins
VIDEO_1, VIDEO_2,
VIDEO_3, SYNC_OUT1,
SYNC_OUT2,
DDC_OUT1, DDC_OUT2
[1]
level 4; contact −8+8 kV
level 4; air discharge −15 +15 kV
IEC 61000-4-2; all other
pins
level 1; contact −2+2 kV
level 1; air discharge −2+2 kV
VCC(VIDEO) video supply voltage −0.5 5.5 V
VCC(DDC) data display channel supply voltage −0.5 5.5 V
VCC(SYNC) synchronization supply voltage −0.5 5.5 V
VI(VIDEO_1) input voltage on pin VIDEO_1 −0.5 VCC(VIDEO) V
VI(VIDEO_2) input voltage on pin VIDEO_2 −0.5 VCC(VIDEO) V
VI(VIDEO_3) input voltage on pin VIDEO_3 −0.5 VCC(VIDEO) V
VI(DDC_IN1) input voltage on pin DDC_IN1 −0.5 VCC(DDC) V
VI(DDC_IN2) input voltage on pin DDC_IN2 −0.5 VCC(DDC) V
VI(SYNC_IN1) input voltage on pin SYNC_IN1 −0.5 VCC(SYNC) V
VI(SYNC_IN2) input voltage on pin SYNC_IN2 −0.5 VCC(SYNC) V
VO(DDC_OUT1) output voltage on pin DDC_OUT1 −0.5 VCC(DDC) V
VO(DDC_OUT2) output voltage on pin DDC_OUT2 −0.5 VCC(DDC) V
Ptot total power dissipation Tamb =25°C - 500 mW
Tstg storage temperature −55 +125 °C
NXP Semiconductors IP4770/71/72CZ16
VGA/video interface
9. Recommended operating conditions
10. Characteristics[1] SYNC outputs unloaded.
[2] Rsync =Rterm +Rbuffer.
[3] Rsync =Rbuffer because Rterm=0Ω.
[4] This parameter is guaranteed by design and characterization.
Table 5. Recommended operating conditionsToper operating temperature −40 - +85 °C
Table 6. Sync circuit characteristicsVCC(SYNC) =5V; Tamb =25 °C; unless otherwise specified.
Supply: pin VCC(SYNC)ICC(SYNC) supply current on pin VCC(SYNC) [1] -- 50 μA
SYNC input at 3V [1] -- 2 mA
Input: pins SYNC_IN1 and SYNC_IN2VIH HIGH-level input voltage 2.0 - - V
VIL LOW-level input voltage - - 0.6 V
Output: pins SYNC_OUT1 and SYNC_OUT2VOH HIGH-level output voltage IOH=1 mA 4.85 - - V
IP4772CZ16; IOH =24mA 2.0 - - V
VOL LOW-level output voltage IOL= 1 mA - - 0.15 V
IP4772CZ16; IOL =24mA - - 0.8 V
Rsync synchronization resistance IP4770CZ16 [2] -55 - Ω
IP4771CZ16 [2] -65 - Ω
IP4772CZ16 [3] -10 - Ω
Sync channeltPLH LOW to HIGH propagation delay CL =50pF; tr and tf≤ 5ns [4] -- 12 ns
tPHL HIGH to LOW propagation delay CL =50pF; tr and tf≤ 5ns [4] -- 12 ns
tr(o) output rise time CL =50pF; tr and tf≤ 5ns - 4 - ns =7pF; tr and tf≤5ns - 1.5 - ns
tf(o) output fall time CL = 50 pF; tr and tf≤ 5ns - 4 - ns =7pF; tr and tf≤5ns - 1.5 - ns
Protection diodeIL(r) reverse leakage current per channel; V= 3.0V - - 1 μA
VBRzd Zener diode breakdown voltage I=1 mA 6 - 9 V
VFd diode forward voltage IF =1mA - 0.7 - V
NXP Semiconductors IP4770/71/72CZ16
VGA/video interface[1] This parameter is guaranteed by design and characterization.
[1] Input VI(DDC_INx)≤ VCC(DDC)−0.4 V and output VO(DDC_OUTx) =VCC(DDC) or
input VI(DDC_INx) =VCC(DDC) and output VO(DCC_OUTx)≤ VCC(DCC)−0.4V.
Table 7. Video circuit characteristicsVCC(VIDEO) =5V; Tamb =25 °C; unless otherwise specified.
Supply: pin VCC(VIDEO)ICC(VIDEO) supply current on pin VCC(VIDEO) static input signals - - 10 μA
Video channel: pins VIDEO_1, VIDEO_2 and VIDEO_3Cch(video) video channel capacitance fi=1 MHz; VI =2.5V [1] --4 pF
Ii(video) video input current VI =VCC(VIDEO) or GND −1- +1 μA
Protection diodeVFd diode forward voltage IF =1mA - 0.7 - V
Table 8. Level circuit characteristicsVCC(DDC) =5V; Tamb =25 °C; unless otherwise specified.
Supply: pin VCC(DDC)ICC(DDC) data display channel supply current - - 10 μA
N-MOSFETIL(off) off-state leakage current [1] -- 10 μA
ΔVon on-state voltage drop VCC(DDC) =2.5 V; VS= GND;
IDS =3 mA - 0.18 V
Protection diodeIL(r) reverse leakage current per channel; V= 3.0V - - 1 μA
VBRzd Zener diode breakdown voltage I=1 mA 6 - 9 V
VFd diode forward voltage IF =1mA - 0.7 - V
