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IP2003
Fully optimized solution for high current synchronous buck multiphase applications in a LGA power block.
International
TOR Rectifier
tPa/Wi"'
TECHNOLOGY
Features:
q Full function multiphase building block
. Output current 40A continuous with no derating up to
TPCB = 100°C and TCASE = 100°C
q Operating frequency up to 1.0 MHz
. Efficient dual sided cooling
q Small footprint low profile (11mm x 11mm x 2.2mm) package
. Optimized for very low power losses
I LGA interface
. Ease of design
q Proprietary packaging enables ultra low Rthi-case top
Description
PD- 96922A
iP2003
Synchronous Buck
Multiphase Optimized LGA Power Block
Integrated Power Semiconductors, Drivers & Passives
iP2003 Power Block
The iP2003 is a fully optimized solution for high current synchronous buck multiphase applications.
Board space and design time are greatly reduced because most of the components required for each
phase of a typical discrete-based multiphase circuit are integrated into a single 11mm x 11mm x 2.2mm
power block. The only additional components required for a complete multiphase converter are a PWM IC, the
external inductors, and the input and output capacitors.
iPOWIR technology offers designers an innovative board space saving solution for applications
requiring high power densities. iPOWIR technology eases design for applications where component integration
offers benefits in performance and functionality. iPOWIR technology solutions are also optimized internally for
layout, heat transfer and component selection.
Pin Function
Supply voltage for the internal circuitry.
When set to logic level high, internal circuitry
of the device is enabled. When set to logic
level low, the PRDY pin is forced low, the
Control and Sychronous switches are turned
off, and the supply current is less than 10pA.
TTL-level input signal to MOSFET drivers.
Power Ready - This pin indicates the status of
ENABLE or VDD. This output will be driven
low when ENABLE is logic low or when VDD
is less than 4.4V (typ.). When ENABLE is
logic high and VDD is greater than 4.4V (typ.),
this output is driven high. This output has a
mm source and lmA sink capability.
Power Ground - connection to the ground of
bulk and filter capacitors.
Switching Node - connection to the output
inductor.
. . Pi # .
iP2003 Internal Block Diagram "l “nVName
2 ENABLE
ENABLE
Driver with 3 PWM
PWM dead time
VDD control
4 PRDY
5, 7 PGND
Input voltage for the DC-DC converter.
11/18/04
International
. TOR Rectifier
iP2003 All specifications @25°C (unless otherwise specified)
Absolute Maximum Ratings:
Parameter Symbol Min Typ Max Units Conditions
VINto PGND V.N - - 16 V
Vroro to PGND VDD - - 6.0 V
PWM to PGND PWM -0.3 - VDD +0.3 V Not to exceed 6.0V
Enable to PGND ENABLE -0.3 - VDD +0.3 V Not to exceed 6.0V
Output RMS Current IOUT - - 40 A Measured at I/sw
Block Temperature TBLK -40 - 125 oC 2t1lttestgrntg over full
Recommended Operating Conditions:
Parameter _Symbol Min Typ Max Units Conditions
Supply Voltage VDD 4.6 5.0 5.5 V
Input Voltage VIN 3.0 - 13.2 V
Output Voltage VouT 0.8 - 3.3 V
Output Current IOUT - - 40 A
Operating Frequency fsw 300 - 1000 kHz
Operating Duty Cycle D - - 85 %
Electrical Specifications tii) VDD = 5V (unless otherwise specified):
Parameter Symbol Min Typ Max Units Conditions
Block Power Loss co PLOSS - 9.4 11.7 W v.N=12v, Vom=1-3V
Turn On Delay © td(on) - 63 - ns Iom=40A, fSW=1MHZ
Turn Off Delay © tum) - 26 - L = 0.3pH
VIN Quiescent Current lo-vm - - 1.0 mA Enable = OV, V|N=12V
Vroro Quiescent Current Iowa - 10 - pA Enable = 0V, VDD=5V
Under-Voltage Lockout UVLO
Start Threshold VSTART 4.2 4.4 4.5 V
Hysteresis VHV5.UVL0 - 150 - mV
Enable ENABLE
Input Voltage High Ihr., 2.0 - - V
Input Voltage Low " - - 0.8
Power Ready PRDY
Logic Level High Vor, 4.5 4.6 - V VDD--4.6V, 'Load=10mA
Logic Level Low VOL - 0.1 0.2 Va,
PWM Input PWM
Logic Level High Vor., 2.0 - - V
Logic Level Low VOL - - 0.8
co Measurement were made using four 10uF (TDK C3225X5R1C106KT or equiv.) capacitors across the input (see
Fig. 8).
© Not associated with the rise and fall times. Does not affect Power Loss (see Fig. 9).
