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IP1202-IP1202TR
Dual Output Full Function 2 Phase Synchronous Buck Power Block, Integrated Power Semiconductors, PWM Controller and Passives.
. PD-94593
International
TOR, Rectifier iP1202
iP(())WWl"" Dual Output Full Function 2 Phase
Synchronous Buck Power Block
Features TECHNOLOGY Integrated Power Semiconductors,
. 5.5V to 13.2V input voltage PWM Control & Passives
. 0.8V to 5V output voltage
. 2 Phase Synchronous Buck Power Block
. 180° out of phase operation
. Single or Dual output capability
. Dual 15A maximum load capability
. Single 2 phase 30A maximum load capability
. 200-400kHz per channel nominal switching frequency
. Over Current Hiccup or Over Current Latch
. External Synchronization Capable
. Overvoltage protection
. Individual soft start per outputs
. Over Temperature protection iP1202 Power Block
. Internal features minimize layout sensitivity *
. Very small outline 15.5mm x 9.25mm x 2.6mm
Description
The iP1202 is a fully optimized solution for medium current synchronous buck applications requiring up to 15A
or 30A. The iP1202 is optimized for 2 phase single output applications up to 30A or dual output, each up to
15A with interleaved input. It includes full function PWM control, with optimized power semiconductor chip-sets
and associated passives, achieving high power density. Very few external components are required to create
a complete synchronous buck power supply.
iPOWlR technology offers designers an innovative space-saving solution for applications requiring high power
densities. iPOWlR technology eases design for applications where component integration offers benefits in
performance and functionality. iPOWlR technology solutions are also optimized internally for layout, heat
transfer and component selection.
iP1202 Configurations
T, Channel1
" Channel 2
Single Output Dual Output
* Although, all of the difficult PCB layout and bypassing issues have been addressed with the internal design of the iPOWIR block, proper layout techniques should be applied
for the design of the power supply board. There are no concerns about unwanted shutdowns common to switching power supplies, if operated as specified. The iPOWIR block
will function normally, but not optimally without any additional input decoupling capacitors. Input decoupling capacitors should be added at Vin pin for stable and reliable long
term operation. See layout guidelines in datasheet for more detailed information.
11/21/03 1
International
. . . . . . . TOR Rectifier
I P 1 202 All specifications @ 25°C (unless otherwise specified)
Absolute Maximum Ratings
Parameter Symbol Min Typ Max Units Conditions
VIN VIN -0.3 - 15
Feedback VFB1/VFB2 -0.3 - 6
Output Overvoltage Sense VFB1sA/FB2s -0.3 - 6
PGOOD -0.3 - 15
ENABLE -0.3 - 15 V
Soft Start SS1/SS2 -0.3 - 6
Vp-ref -0.3 - 6
HICCUP HICCUP -0.3 - 15
SYNC -0.3 - 6
Output RMS Current Per Channel Ioutvsw - - 15 A 2 Independent outputs. See Fig. 3
o Capable of start up over full temperature
Block Temperature TBLK -40 - 125 C range. See Note 1.
Recommended Operating Conditions
Parameter Symbol Min Typ Max Units Conditions
Input Voltage Range V.N 5.5 - 13.2
2 Independent outputs
- - 15 A o .
TPCB = TCASE = 90 C. See Fig. 3
Output RMS Current Per Channel loutvsw 2 Independent outputs
- - 11 A TpCB = 90°C, TCASE = no airflow, no
heatsink. See Fig. 3
0.8 - 5.0 For ba-- 12V
Output Voltage Range om o. 8 - 3.3 V For VIN = 5.5V
Electrical Specifications @ VIN = 12V
Parameter Symbol Min Typ Max Units Conditions
f -300kHz v =12V T = 25°C
P - SW-- , IN , BLK
Power Loss LOSS 7.0 8.75 W VOUT1 = VOUT2 = ISV, IOUT1 = IOUT2= 15A
vIN = 12V, vow: 1.5V
Over Current Shutdown loo - 25 - A fsw = 300KHz, ROCSET = 51.1kS2
HICCUP pin pulled Low
HICCUP duty cycle DHICCUP - 5 - % Chee','. pln pulled high, output short
. " = 12V, I/our = 1.5V,
Soft Start Time tss 5 ms 0581: Css2=0.1pF
Reference Voltage VREF - 0.8 - V
V 3 3 TBLK = -40°C to 125°C, See Note 1.
OUT ACC1 - - - -
VOUT Accuracy - % La-- 12% VOLT :‘5V
V -2 5 - 2 5 TBLK= 0 C to 125 C, See Note 1.
OUT_ACC2 . . v.N= 12v. VOUT = 1.5V
VIN = 12V, Your = 1.5V, specified for
Error Amplifier 2 input offset current share accuracy in parallel
voltage V032 -4 - 4 mV configuration. Rshunt1 = Rshumz=5m9,
lout= 30A. See Fig. 15
FB1/FB2 Input bias current IBFB - -0.1 - pA
Error Amplifier
source/sink Current IERR - 60 - “A
Error Amplifier
Transconductance gm1,gm2 - 2000 - 11th
Output Overvoltage Shutdown See OVP note in Design Guidelines
Threshold OVP - 1.15 x VOL” - V
OVP Fault Propagation Delay tovp - 25 - us Output forced to 1.125Vref
PGOOD Trip Threshold VTh_pGOOD - 0.85 x VOUT V FBI or FB2 ramping down
PGOOD Output Low Voltage VLO_PGOOD - 0.25 - V ISINK=2mA
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