INS8255N ,PROGRAMMABLE PERIPHERAL INTERFACEGeneral Description
The |NSS255 is a programmable peripheral interface
contained in a standard, ..
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INS8255N
PROGRAMMABLE PERIPHERAL INTERFACE
I National
, Semiconductor
November 1980
IN88255 Programmable Peripheral Interface
General Description
The INS8255 is a programmable peripheral interface
contained in a standard, 40-pin dual-in-line package. The
chip, which is fabricated using N-channel silicon gate
technology, functions as a general-purpose parallel
input/output interface in Natiohal Semiconductor':;
8080 microcomputer family. The functional contigura-
signals with the peripheral device. In the third mode
(Mode 2), the INS8255 enables communications with a
peripheral device or structure via one bidirectional 8-bit
bus port (Port A). "Handshaking" signals are provided
over the lines of Port C in this mode to maintain proper
bus flow discipline.
tion of the |N38255 is programmed by the system
software so that normally no external logic is required to
interface peripheral devices.
The INS8255 has three basic modes of operation that
can be selected by the system software. In the first mode
(Mode 0), the INSBZSS provides simple input and
output operations for three 8-bit ports. Data is simply I Outputs Source 1 mA at 1.5 Volts
written to or read from a specified port (Port A, B or C)
without the use of "handshaking" signals. In the second
mode (Mode 1), the INS8255 enables the transfer of . Direct Bit Set/Reset Capability
input/output data to or from a specified 8-bit port . TTL Compatible
(Port A or B) in conjunction with strobes or "hand.
shaking" signals. Ports A and B use the lines of Port C in
this mode to generate or accept the "handshaking" I MICROBUSTM‘ Compatible
Features
I 24 Programmable Input/Output Pins
I Reduces System Component Count
IN38255 MICROBUS Configuration
aoepawl laiaqdyed qqewwefimd ggzssm
ADDRESS
DATA ,
CPO et'-,',,.,-,)
GROUP CONTROL
C cl) Ag A1
07-00 PORT
c,.,".., FIT) A
we on;
__> g msazss
----v RESET FORE
meaomn-g
31°11“ 11’
Typical Diagram of MODE tl operation. The 8 bit ports A, B, C
are defined by the user's program to be either " input at "
output from/to the peripherals.
cii, J t)att9-
'Trademark. National Semiconductor Corp.
qu'FLSMI ‘O/F'rmlea m U s A
"r-Soi-la/
f 1980 Nationai Semiconductor Corp
This Material Copyrighted By Its Respective Manufacturer
DC Electrical Characteristics
T =O°Cto+70°C;V c--+5V4c5%:Vss=OV
Symbol Parameter Min. Typ. Max. Unit Test Conditions
Vc input Low Voltage 0.8 V
VIH Input High Voltage " 2.0 V
VOL Output Low Voltage 0.4 V ' = 1.6 mA
VOH Output High Voltage 2.4 V lore = -50pA (-100uA for BB. Port)
IOHl” Darlington Drive Current 2.0 mA 4 VOH = 1.5 v, REXT = 3909
lcc Power ssppivurrent - - - a 40 mA f W - _ -
NOTE: / tt f t' c; /' A /t f e'
I. Available on 8 pins only of ports B and C, Selected randomly. , f / "i: y A ' - - -
/ ‘5 5. f f r r
AC Electrical Characteristics p' f "
TA = 0°C to +70°C,- Vcc = +5V , 5%, Vss = ov
Symbol Parameter Min. Typ. Max. Unit Test Conditions
tWW Pulse Width of m 400 ns
- _ tDw Time 0.3. Stable before "trv-ri 50 ns
twp Time DB, Stable after WP! 35 ns
tAW Time Address Stable before WR 20 ns
tWA Time Address Stable after ihTii 20 ns
tcsw Chip Select on toirv7i 20 ns
twg Delay from W to Output 500 ns
tRP Pulse Width of 'ro 405 ns
tm EB Set-Up Time 10 ns
tHR Input Hold Time 100 ns ,
tRD Delay from F75 = 0 to System Bus CED ns o'', t' / / " -
tRH Delay from ETD = 1 to System Bus 150 ns
tHZ hm = o to TRl-STATEQOf Bus Drivers 10 150 ns
tAR Time Address Stable before R_I5 50 ns
ICSR Time c-s Stable before FWD 70 ns
tAK Width of Att" Pulse 500 ns
tST Width of gty, Pulse 500 I ns
tps Set-Up Time for Peripheral 60 ns
tpH Hold Time for Peripheral 180 " ns
tRA HoliTime, Address Bus Trailing Edge o ns
mc Hold Time for eT; after R-ty = 1 5 ns
tAD Address Bus Valid to Data Valid 400 ns
tKD Time from m = 1 to Output Floating 20 480 ns
two Time from WiA = 1 to W: = 0 650 ns
tAO Time from A(TK = O to (W: =1 450 ns
tSt Time from g-tTe = o to IBF 450 ns
tm Timefrom FTi5--ltotBF--0 360 ns
tACSO Address Bus Valid to ES 0 ns
tACS1 Address Change to t:Ts OFF 0 ns
This Material Copyrighted By Its Respective Manufacturer
Timing Waveforms
Mode o (Basic Input)
Dt-ot?
At, An
OUTPUY
Mode o (Basic Output)
-.- TST---------
._ , /
_ lPH+
mvur FROM - F- --.-------------------------.---.-------
PERIPHERAL
Ts-----------
Mode 1 (Subbed Input)
This Material Copyrighted By Its Respective Manufacturer
Timing Waveforms (cont'd.)
-----------i;
te-----!-)
em‘)!’
Mode 1 (Strobed Output)
DATA FROM
BOUIIA TO 8255
@xwa—j
Mode 2 (Bidirectional)
-- lps ----v
PERIPNERAL - ----._.--
-- tST
DATA FROM /
PERIPHERAl TO 3255
DATA FROM
3255 T0 PERIPHENAI.
DAYA FROM
MMi TO IDIOA
This Material Copyrighted By Its Respective Manufacturer
INPUT/OUTPUT SIGNALS
Data(D7-Do)Bus,Pins 27-34: This bus comprises eight and B. The system software includes a Bit Set/Reset
TRI-STATE/un/output lines. The bus provides bi. Control Word (see figure) for setting or resetting any of
directional communication between the IN88255 and the eight bits of Port C. When Port C is being used as a
the INS8080A. Data is routed to or from the internal status/control for Port A or B, the Port C bits can be set
data bus buffer upon execution of an OUT or IN or reset by using the Bit Set/Reset Control Word as the
Instruction, respectively, by the INS8080A. In addition, second byte of OUT lnstruction(s).
control words and status information are transferred
through the data bus buffer.
PortA (PA7-PA0), Pins 37-40,1-4: This 8..bit input/ Pin Configuration
output port forms one 8-bit data output latch/buffer U
and/or one 8-bit data input latch. PA] --i 1 an - P114
PA2 .--t. 2 39 - PA5
NOTE _ .. PM - 3 " - PAS
The system software uses a Mode Definition PAo - 4 37 - PA;
Control Word (see figure) as the second byte of mi - 5 Mi - W7i
OUT Instruction(s) to program the functional E - 6 35 - RESET
configuration of Ports A through C. Whenever the END """ 7 M - no
mode is changed, all output registers (and status At - 8 33 - Ot
flip-flops) are reset. Ap - 9 " - "1
PC, - IO msszas 31 - Da
Port B (PB7-PBo), Pins IB-25: This 8-bit input/output PC6 - 11 an - 0.:
port forms one 8-bit data output Iatch/buffer or one PCs - 12 29 - Ds
8-bit data input buffer. PCq - 13 " "-.. 05
P00 - M 27 - 07
Port C (PC7-PC0), Pins10-17: This 8-bit input/output PCI - 15 26 - Vcc
port forms one 8-bit data output latch/buffer or one P02 - Iii 25 - P87
8-bit data input buffer. The port can be split into two ',2, : :3 " - :5
4-bit ports under the mode control. Each of these 4-bit ll' __ 19 i: : It
ports contains a 4-bit latch that may be used for the p82 - 20 21 - P33
control and status signals, in conjunction with Ports A
07 05 " (14 03 02 D1 Du
"sly \__r / PORT A: PORT c MODE PORT B: PORT c
FLAG: 1: INPUT (UPPER): SELECTION: = mp.” (LOWER):
A MODE SELECTION: o = OUTPUT 1= INPUT o-- MODE 0 o= OUTPUT 1= INPUT
I--- ACTIVE 00: MM 0 o = OUTPUT 1= MODE? o: OUTPUT
?}IMSBE} I
- Gnome
't, I /
GROUPA
Mode Definition Control Word Format
[)7 05 D5 B4 D3 D; 01 Du
BIT an
SET/RESET I / \ I / SET/RESET:
FLAG: NOT usgn BIT SELECT: I= SET
u= ACTIVE nun _ n n a RESET
um -- 1
1111 = 3
Bit Set/Reset Control Word Format (Port C Only) "I = 7
. Registered. National Semiconduclor Corp 5
This Material Copyrighted By Its Respective Manufacturer
Operating Modes
Mode 0 (Basic Input/Output)
simply written to or read from a specified port.
Mode 0 Port Definition Chart
In this mode, simple input and output operations for each of the three ports are provided. No "handshaking" is required; data is
Control-Word Bits Group A Group B
No. D, 06 Ds Da Da Dit D, Do Port A I 3;; Port B (:35)
o 1 o o I o o o 0 o OUTPUT OUTPUT OUTPUT OUTPUT
1 1 0 o E 0 o o o 1 OUTPUT OUTPUT OUTPUT INPUT
2 1 o 0 o o o 1 o OUTPUT OUTPUT INPUT OUTPUT
3 1 0 q o 0 o 1 1 OUTPUT OUTPUT INPUT INPUT
4 1 o o o 1 o o o OUTPUT INPUT OUTPUT OUTPUT
5 1 o 0 o 1 o o 1 OUTPUT INPUT OUTPUT INPUT
6 1 o o o 1 0 1 0 OUTPUT INPUT INPUT OUTPUT
7 1 0 o o 1 o 1 1 OUTPUT INPUT INPUT INPUT
*5, _r__co" of 1 o o o 0 INPUT OUTPUT OUTPUT OUTPUT
9 1 o 0 1 0 o o 1 INPUT OUTPUT OUTPUT INPUT
10 1 o o 1 o o 1 0 INPUT OUTPUT INPUT OUTPUT
11 1 0 o 1 0 o 1 1 INPUT OUTPUT INPUT INPUT
12 1 o o 1 1 o 0 0 INPUT INPUT OUTPUT OUTPUT
13 1 0 0 1 1 o 0 INPUT INPUT OUTPUT INPUT
14 1 o o 1 1 o 1 0 INPUT INPUT INPUT OUTPUT
15 1 o o 1 1 o 1 1 INPUT INPUT INPUT INPUT
BASIC INPUT TlMlNG
(07 ' Du FOLLOWS INPUT,
ND LATCHING)
tlr-OO
- ----------- - --
--v --T0ELAY TIME
FROM RD
Dr-Dil :ZZZX )
BASIC OUTPUT
TPMING
(OUTPUTS LATCHED}
LAY TIME
M INPUT DATA
L___7 k..-,.-.-.-,..)
= SETUP VIOLATION
CCL].'.]....].,-.:-...-,..)) _-...---- -
OUTPUT
IDELA "ME
SET UP
Mode o Timing
F**OUTPUT DATA
INVALID
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Operating Modes (cont'd.)
Mode 1 (Strobed Input/Output)
In thismode,a means for transferring input/output data to or from a specified port in conjunction with Strobes or "handshaking"
signals is provided. Port A and Port B use the lines on Port C to generate or accept these "handshaking" signals in Mode l. The
programmer can read the contents of Port C to test or verify the status of each peripheral device. Since no special instruction is
provided in the INS8080A microcomputer system to read the Port C status information, a normal read operation must be
executed to perform this function.
MODE 1 (PORT A) MODE 1 (PORT 8)
PA? »PAn
PA? PA”
TGRC] - l-or-er], -
worslu - STBA l_mots2_)] PCg - $133
----_ INTRA ----itNTRit
M -, PCeJ ---eu-- I/O M
CONTROL WORD C0NTR0LW0R0
070505040302 D10“ Br0ii05040a020i0g
IIIEIIIIIIXEE 1tt&2t2ELlilxl
l = INPUT
t) T OUTPUT
STATUS WORD
D1 05 [15 " 0] D2 Ot Do
Notes:
1. INTEA is controlled by bit set/reset of P04. .10 m) tar. INTEA INTRA mm; ma mm;
2. INTEB IS controlled by bit set/reset of PC2.
': I \ I
GRDUPA unuuv 3
Mode 1 Input
IBE N,
(mvm BUFFER rum ---.a F------
smoa: -.-__
Fi?'-''" Haw PROTECTION
ma mus OPERATION
DATA /
INPUT ---.--. k
INTERNAL
INPUT LATCH - \ _--------.--.---------
Ct) "s:=fcc''
Mode 1 Input Timing
This Material Copyrighted By Its Respective Manufacturer
Operating Modes (cont'th)
MODE I PORT A)
PA; . Mo
TaTa-l
(NOTE lu
MODE I (PORT B)
PBrPBn: c,' y
fii -»
(NOTizu
" INTRA PCO-_ INTRa
ii7i PC4.s WR----o
CONTROL worm CONTROL wunu
070605009302 010!) 07060504 03020100
IIEIIIIIMEK llir;Fr1%E
1 a INPUT
ll : OUTPUT
sutuswonu
Notes: 07 De tls 0.1 D3 01 0. no
l. INTEA is controlled by bit set/reset of PCS. WA [MBA " " INT” INYEB ma mm
2, iNTEB is controlled by bit set/reset of PC2.
DATA BUS
1 Output GRUUPA GROUP]!
INN? -t
F -.--r-
(OUTPUT BUFFER FULL) \
N0 PROTECTION W/O ACK)
at:tt FORTHiS OPERATION
ouwur V- --.---qw---._.----_----.___---.- - _.....---.-.---- ---.
Mode1OutputTiming
PORT A -lSTR08EDlNnlT) PORT A v (smoszo OUTPUT)
PORT a - (smoatn ouwun PORT a - (srnoam mun
PA? - PAa PA7 . PAg
W P04 STBA W PC7 Furr,
PCs mu PCs ERA
PC: INTRA P03 INTRA
PCs] vo P04} l/O
PE7-Pau F37-Pau
7iit PCI W3 To PCg ms
pcz A-CTU, P61 Ian;
PCo INYBa pcu INTRa
CONTROL WORD CONTROL wono
0705050403020109 ty7tlti050a0302010t
-1LiTrtltil1i1l1Cr'(
P65] P04}
t _ INPUT l: :1.iner
. . = = UT
Mode 1 Combinations " o0rpuT
Material Copyrighted By Its Respective Manufacturer
Operating Modes (cont'd.)
Mode 2 (Strobed Bidirectional Bus Input/Output)
This mode enables communication with a peripheral device or structure on a single 8-bit bus for both transmitting and receiving
data (bidirectional bus input/output). "Handshaking" signals are provided to maintain proper bus flow discipline in a manner
similar to Mode 1. In addition, interrupt generation and enable/disable functions are available in Mode 2.
Notes:
I, |NTE1 is controlled by bit set/reset of Pcs.
2. INTE2 is controlled by bit set/reset of P04.
suruswonu
D7 " " " DJ Ot 01 Du
ETFA mm mm. mm mm.
\ I 4\
caourn nnuupa
(DEFINED " MODE l)
irRM00E1SELECTU3N)
irrt--o
Tii5---o
yes - INTRA
“1°.” 2)_l [iii - Tiii,
P024] - l/O
CONTROLWORD
D7D5 D5 " 03 " D100
1 1 1/0l1/0l1/0
___..> 1 -- INPUT
0= OUTPUT
PORT B
------ 1 = INPUT
tl = OUTPUT
GROUP 3 MODE
------i0--M0DE0
I=MODE1
STROBE
DATA HUS
(BETWEEN I/O cmw -------_-.--------
AND IN) BEVICE)
I/O DEVICE - IIO CHIP
Mode 2 Timing
l/O CHIP - l/O DEVICE
This Material Copyrighted By Its Respective Manufacturer
Operating Modes (cont'd.)
- ''co
MODE 2 AND MODE 0 (INPUT)
PC3 .---- INTRA
PA7 PAD
Pc, -----rirF,
P86 ---Ahia
Pc4 ----sts,
Pc5 -r'"'FA
PCZU --il/0
P87 P89
CONTRDLWOHD
o, DE [)5 " 03 02 ul 00
PI:2 [l
l- INPUT
0- OUTPUT
MODE 2 AND MUDE1(0UTPUT)
CONTROL WORD
o, os tos 04 03 ”2 0100
EEK [IE
Mode2Comhinations
MODE 2 AND MODE i) (OUTPUT)
P5793“
C0NTR0L1N0RD
07 thi 05 ths 03 02 n, ”u
IIIIWHIIEII
MODE 2 AND MODE1 [|NPUT)
CONTROL WORD
o, 05 05 o, 03 D2 0100
IIIIEEEIIIIE
la INPUT
0 = OUTPUT
This Material Copyrighted By Its Respective Manufacturer
This Material Copyrighted By Its Respective Manufacturer
|N88255 Programmable Peripheral Interface
Mode Definition Summary Table
Port Mode 0 Mode 1 Mode 2
Bits IN OUT IN OUT Group A Only
PAO IN OUT IN OUT Bidirectional
PA1 IN OUT IN OUT
PA; IN OUT IN OUT
PA:, IN OUT IN OUT
PA4 IN OUT IN OUT
PAs IN OUT IN OUT
PAS IN OUT IN OUT
PA7 IN OUT IN OUT Bidirectional
PB0 IN OUT IN OUT
PB; IN OUT IN OUT
P32 IN OUT IN OUT
PB3 IN OUT IN OUT
(Mode 0 or Mode 1 only)
PB4 IN OUT IN OUT
PB5 IN OUT IN OUT
P36 IN OUT IN OUT
PB7 IN OUT IN OUT
PCO IN OUT INTRB INTRB I/O
PC, IN OUT IBFB ToTsTU U0
P02 IN OUT Tth KEEB vo
PC3 IN OUT INTRA INTRA INTRA
PC4 IN OUT ETEA VO Wii,
PCs IN OUT IBFA VO IBFA
P06 IN OUT v0 KERA K‘RA
PC, IN OUT V0 oisFA o-BT,
Physical Dimensions
..% t _ "TJ, C-'','-.,, .1751; "i'' :5?" _ 5:173.
'35?“ -«
Ceramic Dual-in-Line Package [Cerdip H))
Order Number INS82550
Nallonal Semiconduclor
Crrrporatiort
2900 SermcCprttjuctac Dnve
Santa Clara CA Wi051
Tel (405)737-5000
TWX Nr0)339-9i?40
National Semiconductor GmbH
Eisermtyrnerstrasse " II
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West Germany
Tel (089)57609‘
Telex 05-22772
Miyake Eunldmg
Tokyo Ja pan
Tet t03y355-37 I I
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(Hong Kong) Ltd.
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Cheung Kong Electronic Bldg Jardlm Pauhsjano
4 ng YID Street
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Plastic DuaI-in-Line Package (N)
Order Number INSBZSSN
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Cable NATSEM}
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This file is the datasheet for the following electronic components:
INS8255N - product/ins8255n?HQS=T|-nu|I-null-dscatalog-df-pf-null-wwe
