INS8060N ,SINGLE-CHIP 8-BIT N-CHANNEL MICROPROCESSOR (SC/MP FAMILY)features in conjunction with the low initial
cost describe what SC/MP really is - a microprocessor ..
INS8251N ,7 V, programmable communication unterfaceFeatures
The INS8251 is a programmable Universal Synchronous/ . Synchronous and Asynchronous Full ..
INS8255N ,PROGRAMMABLE PERIPHERAL INTERFACEGeneral Description
The |NSS255 is a programmable peripheral interface
contained in a standard, ..
INT100S , Low-Side and High-side Drive with Simultaneous Conduction Lockout
INT100S , Low-Side and High-side Drive with Simultaneous Conduction Lockout
INT200PFI1 , Low-side Drive and High-side Control with Simultaneous Conduction Lockout
IRFS740B ,400V N-Channel MOSFETIRF740B/IRFS740BNovember 2001IRF740B/IRFS740B400V N-Channel MOSFET
IRFS740B ,400V N-Channel MOSFETFeaturesThese N-Channel enhancement mode power field effect • 10A, 400V, R = 0.54Ω @V = 10 VDS(on) ..
IRFS820B ,500V N-Channel MOSFETFeaturesThese N-Channel enhancement mode power field effect • 2.5A, 500V, R = 2.6Ω @V = 10 VDS(on) ..
IRFS830A , Advanced Power MOSFET
IRFS830A , Advanced Power MOSFET
IRFS830B ,500V N-Channel MOSFETIRF830B/IRFS830BNovember 2001IRF830B/IRFS830B500V N-Channel MOSFET
INS8060D-INS8060N
SINGLE-CHIP 8-BIT N-CHANNEL MICROPROCESSOR (SC/MP FAMILY)
I National
i Semiconductor
Microprocessor (SC/MP Family)
General Description
The INS8060 is the N-channel version of National's
SC/MP family (an acronym for Simple, Cost-effective
Microprocessor). This family consists of single-chip,
8-bit microprocessors packaged in standard 40-pin
dual-in/ine packages. N-channel, silicon gate, deple-
tion mode standard-process technology gives the
thlS8060 high performance, high reliability, and high
producibility.
The INSBOGO SC/MP is intended for use in general-
purpose applications where cost per function is a
most significant criterion. But cost efficiency is only
a part of SC/MP's story. It goes on to include a
variety of useful functions that are not even provided
by some of the expensive microprocessors, like self-
contained timing circuitry, 16-bit (65k) addressing
capability, serial or parallel data-transfer capability
and common memory/peripheral instructions. The
built-in features in conjunction with the law initial
cost describe what SC/MP really is - a microprocessor
specifically designed to provide the simplest and most
efficient solution to many application requirements.
Customer Benefits
I Simpler interfacing
q Bidirectional TRIASTATEG 8-bit data bus
I TTL-compatible input/output interface
Block and Connection Diagrams
Aounzss =ts ADDRESS "
(mam (lOW)
PDINTERS Pomnzns
(HIGH) (LOW)
INCREMENTER A“ZUMULMOR
xts EXTENSION cts
REGISTER
xfs STATUS w
REGISTER
l/DCDNTROL
ft u d
INSTRUCTION
DECODE AND -
CONTROL
INSTRUCTION DATA I/O Q
REGISIER REGISTER I
OSCILLATOR
INSBOGO Single-Chip 8-Bit N-Channel
JANUARY 1978
PUB. NO. 426305290-001 C
. Si-gate N-channel ion-implant process
I Direct Memory Access (DMA) and multiprocessor
capabilities
I Handshake bus-access control on chip
I Simplified programming
I Multiple addressing modes I program-counter-
relative, immediate data, indexed, auto-indexed,
and implied
I Direct control output
I Three user-accessible controI-flag outputs
I Simpler l/O hardware
I Separate seriaI-data input and output ports
I Two sense inputs
I Direct interfacing to standard memory parts
I Simplified timing hardware
. On-chip clock generator
I Interface flexibility
I Capability to interface with memories or peri-
pherals of any speed
I Large system capability
I Address capability to 65k bytes of memory
I Simplified power requirements
I Single 5-volt supply
I Low power
I Lower cost
. Plastic package
1519 0(06'
ans -l- , van
NRDS -i' _ NADS
NENIN -a' ' XDUT
NEMOUT -r Tr XIN
NSREO -'"'ii" '? A011
NHOLD -r ? A010
NRST I-T TC ADDS
CONT -r Ti- A008
MI _10. "ii- ADI]?
DES T T ADDS
DES T ? ADOS f
BM T -iii- ADM
083 7- Tr" A003
082 7 T A002
D81 -f?i'" "rs" A001
[130 -Tr T A000
SENSE-A T Tr MN
SENSE-E -tsT' T SHUT
FLAG D T T FLAG 2
GND - - FLAG I
INSBOSO Pin Configuration
l) 1977 National Semiconductor Corp.
} C)/VB20N118/Prirnted in U.S.A.
(Kuwea dW/OS) Jossaooidomiw Ieuueuo-N 1!8-8 diuo-aifiuvs ogoesm
Applications
I Test Systems and Instrumentation
. Machine Tool Control
0 Small Business Machines
I Word Processing Systems
I Educational Systems
I Multiprocessor Systems
Process Controllers
Terminals
Traffic Controls
Laboratory Controllers
Sophisticated Games
Automotive
Absolute Maximum Ratings (Note 1)
Voltage at Any Pin ............. -0.51/ to +7.0V
Operating Temperature Range ........ fc to +70°C
Storage Temperature Range ....... -6tioC to +150°C
Lead Temperature (Soldering, 10 seconds) ..... 300°C
DC Electrical Characteristics; = 00c to +70°C, vcc = +5V i 5%)
Parameter Conditions Min. Max. Units
INPUT SPECIFICATIONS
All Input Pins Except VCC and GND
Logic "1" Input Voltage 2.0 VCC V
Logic "0" Input Voltage -0.5 0.8 V
Input Capacitance
(All pins except VCC and GNDI 10 pF
Supply Current TA = 25°C
ICC outputs unloaded 45 mA
TA = 0°C
outputs unloaded 50 mA
OUTPUT SPECIFICATIONS
"TRI-STATE' Pins (NWDS, NRDS,
DBO-DB7, ADOO-ADI 1)
Logic ''l''Output Voltage IOUT = ~100pA 2,4 V
Logic "0" Output Voltage IOUT = 2.0mA 0.4 V
NADS, FLAG 0 - 2, SOUT, NENOUT
Logic "1" Output Voltage 'OUT = -100PA VCC _ 1 V
Logic "I" Output Voltage 'OUT = -1mA 1.5 V
Logic "0" Output Voltage 'OUT = 2.0mA 0.4 V
NBREO (Note 2)
Logic "O'' Output Voltage IOUT = 2.0mA 0.4 V
Logic "I'' Output Current 0 < VOUT < VCC 110 yA
Logic "I" Output Voltage 'OUT = -100PA 2.4 V
Logic "O'' Output Voltage 'OUT = 1.6mA 0.4 V
AC Electrical Characteristics [TA = 0°C to +7o°c, Vcc = +5v , 5%, 1 TTL Load (Note 3)]
Parameter Conditions Min. Max. Units
fx 0.1 4.0 MHz
R = 2409 t 5% (figure 23) 2.0 4.0 MHz
C = 300pF i 10%
TC (Note 4) 500 ns
Microcycle 1 us
External Clock Input (see figure 2A)
TWO 120 ns
Tw1 120 ns
XOUT/ADS Timing Relationship
(see figure 3)
TH (ADS) 100 225 ns
Address and Input/Output Status
(see figures 5 and 6)
T01 (ADS) 3Tc/2 ns
Tw (ADS) (Tc/2) - 50 ns
Ts (ADDR) (TC/2) -165 ns
TH (ADDR) 50 ns
Ts (STAT) (TC/2) -150 ns
TH (STAT) 50 ns
TH (NBREO) 0 ns
Data Input Cycle (see figure 5)
TD (R DS) 0 ns
Tw (RDS) TC + 50 ns
Ts (RD) 175 ns
TH (RD) 0 ns
TACC (RD) 2Tc - 200 ns
Data Output Cycle (see figure 6)
TD (WDS) Tc - 50 ns
Tw (WDS) Tc ns
Ts (WD) {Tc/2) - 200 ns
TH (WD) 100 ns
Input/Output Cycle Extend
(see figure 7)
Ts (HOLD) 200 ns
TDI (HOLD) 130 275 ns
T02 (HOLD) 350 ns
Tw (HOLD) oo ns
TH (HOLD) 0 ns
Bus Access (see figure 4)
TD (NENOUT) 150 ns
T02 (ADS) Tc/2 3Tc/2 ns
TH (N ENIN) 0 ns
Output Load Capacitance
XOUT 30 pF
All Other Output Pins 75 pF
Note 1: Maximum ratings indicate limits beyond which damage may occur. Continuous operation at these limits is not intended and should be
limited to those conditions specified under electrical characteristics.
Note 2: NBREQ is an input/autput signal that requires an external resistor to Vcc.
Note 3: All times measured from valid Logic "0" level = 0.8 V or valid Logic "1''level = 2.0 V.
Note 4: TC is the time period for two clock cycles of the on-chip or external oscillator (TC = 2/fxl. Refer to paragraph titled Timing Control
for detailed definition.
Note ti: All times measured with a 50% duty cycle on the external clock.
Functional Description
SC/MP Isa selfrcontained generaI-purpose microprncuwu
designed for ease of implementation in standalone! DMA
(Direct Memory Access). and multiprocessor apphcatmns.
Communications between SC/MP and external memory!
peripheral devices are effected via a 12-bit dedicated
address bus and an frbit hidnectional data bus. During
the address interval of each input/output cycle, SC/MP
employs both busses to provide a 16-bit address output:
the 12 least significant address bits are sent out over the
12-bit address bus and the 4 most significant address hits
are sent out over the 8-bit data bus along with 4 status
jts. Separate strobe outputs from SC/MP (NADS,
NWDS, NRDS} indicate when valid address information
IS present on the two hussua, and when valid Input!
output memory or peripheral data are present on the
84m bus. To further extend flexthilitv of apphcatton,
serial data input/output ports are also provided so that
serial data transfers can be effected under program
control. The remairdny input/output Signals shown in
figure 1 are dedicated to generai-puruose control and
status functions, Including imtiallzatlon, bus manage-
ment, microprocessor halt, utterrupt request, input;
output cycle extension, and usrerspecdied hardware/
software Interface functions‘ A detailed descmmon of
each input/output srgrnal is provided in table 1.
ADURESS E lt BIT
E. t )0 ADDRESS
:D ':2lC_Cy n
n . I tl If A ll I l n l J n I fil
r-"'-s A - n f
OUIPUI nuaniss DUTPUT Aonness tz)
(mum (LOW)
A PROGRAM comma macaw COUNTER ‘(m Gun
f, (HIGH) E a (ant -
E S s, t
; P0)NTERREt1lSTErll E G' POINTER REGISTERI e
3 (HIGH) i' a now) §
: a 'td --v t:
E P0lNTERRElhSTERt If, E POINTER REGISTER? g
a mom a: a tum] "-
P0lNTERREGlSTER3 e0lNTERREGISTEft3
mmm uowl
um 4: Bus TRANSFER
INCREMENIER AND SHIFT
xm EDS-- OSCILLATOR ACCUMULAIDR =
E} AND -
XEIUT Err------ nwwnnm. F"-"-"-'''- ---EXTENSION
l NBREO Li>---- xts REGISTER b
"""l E f
NENOUT Ei>-
.rr _ ii)
mm” Eh- corhunm $00T
SENSE m
A Esh----- -DATA N as INTERR0PT
" ~qu E>--- " '" --NRDS Ci>-- STATUS
- REGISTER
ll ll cntmn AND l,
- Funcnow FLAG a
CONT CONTROL +ED INSTRUCTION --ael FLAGZ
DECODE I/0 smug -
comm m
wast I7 >
msmucnon 0ATA Ira
REGISTER REGISTER .
s-an DATAI/O
FIGURE 1. INS8060 Detailed Block Diagram
TABLE 1. Input/Output Signal Description
Signal
Mnemonic
Functional Name
Description
NENOUT
SENSE A
SENSE B
0, 1, 2
Reset Input
Continue Input
Bus Request Input/Output
Enable Input
Enable Output
Address Strobe Output
Read Strobe Output
Write Strobe Output
Input/Output Cycle Extend
Sense/lnterrupt Request
Sense Input
Serial Input to E Register
Serial Output from E
Register
Flag Outputs
Address Bit 00 through
Address Bit 11
Set high for normal operation. When set low, aborts in-process
operations. When returned high, internal control circuit zeroes
all programmer-accessible registers; then, first instruction is
fetched from memory location 000116.
When set high, enables normal execution of program stored in
external memory. When set low, SC/MP operation is suspended
(after completion of current instruction) without loss of internal
status.
Associated with SC/MP internal allocation logic for system bus.
Can be used as bus request output or bus busy input. Requires
external load resistor to Vcc.
Associated with SC/MP internal allocation logic for system bus.
When set low, SC/MP is granted access to system busses. When
set high, places system busses in high-impedance (TR!-STATE®)
Associated with SC/MP internal allocation logic for system bus.
Set low when NENIN is low and SC/MP is not using system
busses (NBREO-high). Set high at all other times.
Active-low strobe. While low, indicates that valid address and
status output are present on system busses.
Active-low strobe. On trailing edge, data are input to SC/MP from
8-bit bidirectional data bus. High-impedance (TRI-STATE®)
output when input/output cycle is not in progress.
Active-Iow strobe. While low, indicates that valid output data are
present on 8-bit bidirectional data bus. High-impedance (TRI-
STATE®) output when input/output cycle not in progress.
When set low prior to trailing edge of NRDS or NWDS strobe,
stretches strobe to extend input/output cycle; that is, strobe is
held low until NHOLD signal is returned high.
Serves as interrupt request input when SC/MP internal IE
(Interrupt Enable) flag is set. When IE flag is reset, serves as user-
designated sense condition input. Sense condition testing is
effected by copying status register to accumulator.
User-designated sense-condition input. Sense-condition testing is
effected by copying status register to accumulator.
Under software control, data on this line are right-shifted into E
register by execution of SIO instruction.
Under software control, data are right-shifted onto this line from
E register by execution of SIO instruction. Each data bit remains
latched until execution of next SIO instruction.
User-designated general-purpose flag outputs of status register.
Under program control, flags can be set and reset by copying
accumulator to status register.
Twelve TRi-STATE® address output lines. SC/MP outputs 12
least significant address bits on this bus when NADS strobe is low.
Address bits are then held valid until trailing edge of read iNRDS)
or write (NWDS) strobes. After trailing edge of NRDS or NWDS
strobe, bus is set to high-impedance (TRl-STATE®) mode until
next NADS strobe.
The 8-bit bidirectional data bus is set to the high-impedance (TRl-STATEO) mode except when it is actually in
use by SC/MP (NADS, NRDS, or NWDS low). During the addressing interval of each input/output cycle (NADS
low), SC/MP provides address and status outputs over the bus; during the ensuing data-transfer interval (NRDS or
NWDS low], 8-bit input or output data bytes are routed over the bus.
TABLE 1. Input/Output Signal Description lConILnued)
Signal Mnemonic/ Output at NA0__S_ Time Input at Output at
Pin Designation Functional Name Description NRDS Time NWDS Time
DBO Address Bit12 Fourth most significant bit of 16-bit
address.
DBI Address Bit13 Thirdmustsignihcantbitof16bit
address.
DB2 Address Bit 14 Second most significant bit of 16-bit
address. Input data Output data
DB3 Address Bit 15 Most significant bit of 16-bit address. are expected are valid
DB4 R-Flag When high, data input cycle is start- Ir," the eight on the eight
ing; when low, data output cycle is _(, BO'DBN 99800877
starting. lines. lines.
DB5 l-Flag When high, first byte of instruction
is being fetched.
DB6 D-Flag When high, indicates delay cycle is
starting; that is, second byte of DLY
instruction is being fetched. - _ -- - _ i -
DB7 H-Flag When high, indicates that Halt Note: The DB0 through DB7
Instruction has been executed. (In (ADITHFLG) lines are a
some system configurations, the H- high-impedance (open circuit)
Flag output is latched and, in load when SC/MP does not
conjunction with the CONTinue have access to the input/
input, provides a programmed halt.) output bus.
DRIVERS AND RECEIVERS
Equivalent circuits for SC/MP drivers and receivers are
shown below. All inputs have static charge protection
circuits consisting of an RC filter and voltage clamp.
These devices still should be handled with care, as the
protection circuits can be destroyed by excessive static
charge.
TIMING CONTROL
All necessary timing signals are provided by a three-stage
inverter ring oscillator contained on the SC/MP chip.
Two control pins, XIN and XOUT, permit the frequency
of the oscillator to be controlled by any of the following
methods:
1. By leaving the XOUT pin unterminated and driving
the XIN pin with an externally generated TTL clock
that conforms to the parameters shown in figure 2A.
For this method, the frequency of the oscillator is
equal to the frequency of the external clock input.
2, By connecting a resistor-capacitor feedback network
between the XIN and XOUT pins and GND as shown
3. By connecting a crystal with low-pass filter network
between the XIN and XOUT pins and GND as shown
in figure 2C (for above 1 megahertz) or figure 20 (for
1 megahertz or below). For this method, the frequency
of the oscillator is equal to the resonant frequency of
the crystal and the low-pass filter prevents unwanted
In addition to illustrating appropriate frequency-control
networks for the on-chip oscillator, figures 2A through
20 also show how an optional driver may be used. to
derive a system clock from the oscillator signal present
at the XOUT pin. For reference purposes, the timing
relationship between the XOUT signal and the NADS
RECEIVER nmvsn
.F Vcc 7
mm -H I
CONT i I uwos
's11 A qb-EFu-l , ms
SEN n l T -I cm) i’
l , GND Vcc
NENIN l --i i233
UT _ .
NHOLD I I m: 0-2 In figure 2B.
, "t l SOUT
GND GND I
1 GND _ CC 5
NBREu --C7> 00-07
_ F-ss GND GND l
1 GND "I' _
cc-a-) -H ADDR 0-11 harmonic oscillations.
GND GND l
5 vet: 1
i -I I
i xout
i --l END )
k ------------------- J
= INPUT -
mpnnncnom “10% I
GND strobe is shown in figure 3.
|N88060 Driver and Receiver Equivalent Circuits
In the discussions that follow, instruction execution and
input/output timing are described in terms of microcycles.
The time interval of a microcycle is four times the period of the oscillator; that is:
period of one microcycle = 2TC
TC = 2r,,,1-ep = 2tl-,c) = 2(z-1-..-)
DSC res
where:
Tc = time period for two cycles of on-chip or external oscillator
fosc = frequency of on-chip oscillator
fres = resonant frequency of crystal connected between XIN and XOUT pins
f - frequency of external clock applied to XIN pin
A. External Clock Input
DRIVER
EXTERNAL
CLOCK XIN
OPTIONAL
DRIVER SC/MF
OPTIONAL "
SYSTEM -----1: F--- XOUT
BLOCK "
EXTERNAL CLOCK PARAMETE RS
’4Tw1>1
'ir-ra,--)
B. Resistor-Capacitor Feedback Network
xm xoru1
UPTDUNAL
DRIVER
n ft " 0911mm
4 'U. -- SYSTEM
" CLOCK
l: l N0TE:1il0saRs;2k
Typical Oscillator Frequency
vs RC Time Constant
RC TIME CONSTANT (ns)
u 0.2 0.4 m; 0.8 1.0 1.2 1.4 1.5 La 2.0
CLOCK PERIOD thHz)
FIGURE 2. Frequency Control Networks for Cht-Chip Oscillator
C. Crystal with Low-Pass Filter (Above 1MH2)
XI XOUT
OPTIONAL
DRIVER
" OPTIONAL
l) --l _ SYSTEM
" CLOCK
Suggested values for Crystal with Low-Pass Filter Network.
Crystal RP C1 R1
2MHz 100k$2 56PF Ikf2
3.58MH2 100KC2 27pF 1IG2
4MHz 100kf2 27pF lkC2
XTAL is parallel resonant with maximum series resonance equal
to 1 kn.
D. Crystal with Low-Pass Filter " MHz or Balowl
MN xour
OSEONAL
Rt R2 b. OPTIONAL
[I " J." .... SYSTEM
" CLOCK
-- --TH (ABS)
FIGURE 3. XOUTINADS Timing Relationship
INSTRUCTION FORMAT
The SC/MP instruction repertoire includes both single-
byte and double-byte instructions. A single-byte instruc-
tion consists of an 8-bit operation code that specifies an
operation that SC/MP can execute without further
reference to memory. A double-byte instruction consists
of an 8-bit operation code and an 8-bit data or displace-
ment field. When the second byte represents a data field,
the data are processed by SC/MP during execution of the
instruction, thereby eliminating the need for further
memory references. When the second byte represents
a displacement value, it is used to calculate a memory
address that will be accessed {written into or read from)
during execution of the instruction (refer to Addressing).
DATA STORAGE
As shown in figure l, SC/MP provides ten internal
registers, seven of which are accessible to the program-
mer. The purpose and function of these registers are
described below.
Program Counter - The program counter is a 16-bit
register that contains the address of the instruction being
executed. The contents of this register are automatically
incremented by one just beforeeach instruction is fetched
from memory to enable sequential execution of the
stored instructions. Under program control,the contents
of this register also may be modified or exchanged with
the contents of a pointer register to effect subroutine
calls and program branches.
The 15-bit address output of the program counter
consists of a 4-bit high-order address and a 12-bit
low-order address. When the program counter is
incremented at the start of each instruction fetch
input/output cycle, only the 12 low-order bits are
affected; no carry is provided to the 4 high-order
bits. For systems employing memories of 4k or
less, the high-order bits can be ignored as they are
set to 000016 following initialization. For systems
employing larger memories, the contents of a
pointer register can be modified to select the
desired 4k block of memory.
Pointer Registers - The pointer registers are 16-bit
general-purpose registers that normally are loaded under
program control with reference addresses that serve as
page pointers, stack pointers, and subroutine pointers. In
applications having minimal memory addressing require-
ments, these registers may be used alternately as data
storage registers.
When interrupt requests are enabled, pointer
register 3 is automatically referenced by the internal
microprogram for formation of the starting address
of the user-generated interrupt service routine.
(See figure 9.) In this case, the contents of pointer
register 3 must be set to one less than the memory
location of the first instruction in the interrupt
service routine.
Accumulator - The 8-bit accumulator (AC) is the pri-
mary working register of SC/MP. It is used fot performing
and storing the results of arithmetic and logic operations
as well as for data transfers, shifts, rotates, and data
exchanges with the program counter, the pointer regis-
ters, and the status register.
Extension Register - The extension register is used both
for serial input/output data transfers and with the
accumulator to effect arithmetic, logic, and data-transfer
operations, If the second byte of an indexed or auto-
indexed memory-reference instruction (refer to Addres-
sing) equals 42810, the contents of the extension
register are used as the displacement value for address
formation.
Status Register _ The status register provides storage for
arithmetic, control, and software status flags. For more-
detailed information on the function of this register,
refer to Status Register under the description of the
Arithmetic and Logic Unit.
Instruction Register - The 8-bit instruction register is
not accessible to the programmer. During the fetch phase
of each instruction cycle, this register is loaded with the
8-bit instruction operation code retrieved from memory
(for a single-byte instruction or the first byte of a
double-byte instruction).
Data Input/Output Register - The data input/output
register is not accessible to the programmer. It is used for
temporary storage of all input/output data received via
or transmitted over the 8-bit bidirectional data bus
during the data-transfer interval of each input/output
cycle (NRDS or NWDS low).
Address Register - The 16-bit address register is not
accessible to the programmer. It is used for temporary
storage of the 16-bit address transmitted during an input/
output cycle.
ARITHMETIC AND LOGIC UNIT
The Arithmetic and Logic Unit (ALU) provides the data-
manipulation capability that is an essential feature of
any microprocessor. The operations provided by the
ALU include OR, XOR, increment, decrement, binary
addition, and decimal addition. For decimal addition,
the data inputs to the ALU are treated as two 4-bit BCD
digits, thereby eliminating the program-storage and
execution time required to perform BCD to binary
conversion.
BUS TRANSFER LOGIC
The bus transfer logic processes the gating and function
control outputs of the instruction-decode logic to
provide the shift-right (with link, without link, or with
serial input data), rotate (with or without link), and
bus-exchange functions necessary for data movement
between the SC/MP internal read and write busses. A
general summary of the data-manipulation capabilities
available to the programmer follows.
1. Either the Iow-order or the high-order byte of any
pointer register can be exchanged with the contents of
the 8-bit accumulator. Thus, data exchanges between the
pointer registers can be effected one byte at a time via
the accumulator.
2. The contents of the program counter can be directly
exchanged with the contents of any pointer register.
3. The contents of the extension register can be loaded
into the accumulator or can be exchanged with the
contents of the accumulator, When the accumulator is
loaded from the extensum register, the original contents
of the accumulator are lost.
4. The contents of the status register can be copied into
the accumulator to enable status modification or condi.
tional-branch testing. When the status register is copied
into the accumulator, the contents of the status register
are not altered but the original contents of the accumu-
lator are lost.
5. The contents of the accumulator can be copied into
the status register to change the outputs of the status
register, except for status bits 4 and 5 (Sense A and B
inputs to SC/MP). Since these are read-only bits, they
are not affected by data movements internal to SC/MP.
Copying the accumulator into the status register does
not alter the contents of the accumulator.
The flag 0, l, and 2 outputs of the status register
serve as latched flags; in other words, they.are set
to the specified state when the contents of the
accumulator are copied into the status register, and
they remain in the specified state until the contents
of the status register are modified again under
program control.
STATUS REGISTER
The function of each bit in the status register is described
briefly below.
7 6 5 4 3 2 1 0
CY/L ov SB SA IE F2 F1 F0
User Flag 0 - User-assigned generaI-purpose status bit for
implementation as software status bit or in system
control applications. This status bit is available as an
external output from SC/MP.
User Flag1 - Same as User Flag 0.
User Flag 2 - Same as User Flag 0.
Interrupt Enable Flag - Internal status bit that is set
and reset under program control. When set, SC/MP
recognizes external interrupt requests received via Sense
A input. When reset, inhibits SC/MP from recognizing
interrupt requests.
Sense A - General-purpose status input for sensing
external conditions. When IE flag is reset, this bit can be
tested by copying status register to accumulator. When
IE flag is set, this bit serves as interrupt request input
causing SC/MP to automatically branch to user-generated
iroterrtipt-service routine in response to high input.
Sense B - Same as Sense A except that it is not tested
for interrupt status.
Sense A and B inputs are read-only bits. Thus, they
are not affected when the contents of the accumu-
lator are copied into the status register.
Overflow (0V) - This bit is set if an arithmetic over-
flow occurs during an add (ADD, ADI, or ADE) or a
complement-and-add instruction (CAD, CAI, or CAE).
It is not affected by the decimal-add instructions (DAD,
DAI, or DAE).
Carry/Link (CY/L) - This bit is set if a carry from the
most significant bit occurs during an add, complement-
and-add, or decimal-add instruction. Thus, it serves as a
carry input to the next add instruction. In addition, it is
included in the Shift Right with Link (SRL) and Rotate
Right with Link (RRL) instructions.
CONTROL
The operation of the SC/MP microprocessor consists of
repeatedly accessing or fetching instructions from the
program stored in external memory and executing the
operations specified by the instructions. These two steps
are carried out under the control of an internal micro-
program. ISC/MP is not user-microprogrammable.) The
microprogram is similar to a state table specifying the
series of states of system control signals necessary to
carry out each instruction. Microprogram storage is
provided in the instruction decode and control logic,
and microprogram routines are implemented to fetch
and execute instructions. The fetch routine first incre,
ments the program counter, and then causes the instruc-
tion address to be transferred from the program counter
to the system busses via the output address register. The
microprogram next initiates an input data transfer. When
the instruction operation code is subsequently placed on
the 8-bit data bus (single-byte instruction or first byte
of double-byte instruction), the operation code is loaded
into the instruction register. The operation code is then
partially decoded to determine whether the instruction
contains a second byte. If it does, a second input data
transfer is effected to load the next byte in the data
input/output register.
After the complete instruction is stored in the instruc-
tion and/or data input/output register(s), the instruction
decoder transforms the instruction operation code into
the address of the appropriate instruction-execution
routine contained in the internal microprogram. The
microprogram then branches to the specified internal
address to initiate execution of the instruction. The
resulting execution routine comprises one or more
microinstructions that implement the required functions.
For example, the first microcycle of an Extension
Register Add Instruction (ADE) causes the contents of
the extension register to be gated onto the read bus.
transferred to the write bus via the bus control logic,
and then written into the data input/output register.
The next microcycle causes the contents of the accumu-
lator to be gated onto the read bus, the contents of the
read bus to be added to the contents of the data input/
output register via the ALU, and the resultant output of
the ALU to be written into the accumulator via the
write bus. The final step of the execution routine is a
jump back to the fetch routine to access the next
instruction.
INITIALIZATION
Since SC/MP may power up in a random condition, the
following power-up and initialization procedure is
recommended.
l, Apply power (GND and Vcc) and set NRST low.
Allow ample time (typically, 250ms) for the
oscillator and the internal clocks to stabilize. In
systems where NRST is set low after turning on
power, NRST must remain low for a minimum of
4TC. While NRST is low, any in-process opera-
tions are aborted automatically. When NRST is
low, strobes and address and data busses are in the
Non-I/O state (high-Z state).
2. Set NRST high. If the rise time of this input is too
slow, the processor, first, will initialize and execute a
few instructions and, then, will reinitialize. if the applica-
tion is such that multiple initialization is undesireable,
NRST should be brought high at a minimum rate of 2
volts per microcycle.
This causes the SC/MP internal control circuit to
set the contents of all programmer-accessible
registers to zero, Thus. when SC/MP is granted
access to the system busses following initialization,
the first instruction is fetched always from memory
location 000116. The NBREQ output goes low,
indicating the start of this input/output cycle; this
Occurs at a time within 13TC after NRST is set
high. Normal execution of the program continues
as long as NRST remains high.
Parallel Data Transfers
Parallel data transfers occur during each instruction
fetch and during the ensuing read/write cycle associated
with execution of the memory-reference instructions.
This class of instruction could perhaps more properly be
called the "Input/Output Reference Class" in the case of
the SC/MP microprocessor, since all data transfers,
whether with memory, peripheral devices, or a central
processor data bus, occur through the execution of these
instructions. This unified bus structure is in contrast
with many other microprocessors and minicomputers
that have one instruction type (input/output class) for
communication with peripheral devices and another
instruction type [memory reference class) torcommuni-
cation with memories. The advantage of the approach
taken by'SC/MP is that a wider variety of instructions
(the entire memory-reference class) is available for
communications with peripherals. Thus, the LD and ST
(Load and Store) instructions can be used for basic
transfers, the lLD and DLD (increment/decrement and
load) instructions can be used for indexing peripheral
registers, and the remaining memory reference instruc-
tions can be used, as required, for "one-step'' retrieval
and processing of peripheral input data.
BUS UTILIZATION
The bus utilization of SC/MP is shown in table 2.
NBREO, NENlN, and NENOUT are active and bus
access is controlled as' shown in figure 4. If NENIN is
returned high during an input/output cycle, the input/
output cycle is repeated when NENIN is again returned
During an lLD or DLD instruction, SC/MP does not
relinquish the bus between the loading of the data and
the storing of the modified data. If NENIN is brought
high after the data have been loaded, the load portion of
the cycle is not repeated when NENIN is returned low.
BUS ACCESS
Before SC/MP can initiate parallel data transfers with
memory or peripheral devices, it must have access to the
system address and data busses. Three of the SC/MP
input/output signals are associated with bus control:
NBREO, NENIN, and NENOUT. For simple stand-alone
applications, the NENOUT signal can be ignored and the
NENIN signal can be tied to GND to allow the SC/MP
microprocessor to have continual access to the.systern
busses. The NBREO input/output line then goes low
during each input/output cycle as shown in figures 5 and
6 to indicate when SC/MP is actually using the system
busses.
The NBREO input/output line must be tied to
VCC via an external load resistor to allow normal
operation of the SC/MP microprocessor.
For DMA and multiprocessor applications, the NBREO,
NENIN, and NENOUT signals can be interconnected in
various configurations to allow bus access to be granted
to requesting devices according to user-specified priori-
ties. Figure 4 illustrates the general sequence in which
these signals are processed by SC/MP to gain access to
the system busses and to indicate when the busses are
actually being used.
INPUT/OUTPUT CYCLE
Once SC/MP has control of the system busses, the actual
input/output cycle begins. As shown in figures 5 and 6,
the functions of memory addressing, data reading, and
data writing are implemented, respectively, by the address
strobe (NADS), the read strobe (NRDS), and the write
strobe lNWDS). Note that the NBREO signal is reset
high at the end of the input/output cycle to indicate
that the system busses are now free for use by the
highest-priority requesting device.
The first operation that SC/MP performs for each input/
output cycle is to load the 12 least significant address
bits onto the 12-bit address bus, and the 4 most signifi-
cant address bits along with 4 status bits onto the 8-bit
data bus. At the same time, SC/MP sets the NADS output
low to indicate that the address and the status informa-
tion are valid. The low-order address on the 12-bit bus is
then held valid for the duration of the input/output
cycle; the high-order address and the status information
on the 8-bit bus remain valid only while NADS is low.
While valid, the status bits have the following signifi-
cance:
RFLG - When high, indicates that input/output cycle is
read eycle;when low, indicates that input/output cycle is
write cycle.
IFLG - Set high to indicate that instruction operation
code (single-byte instruction or first byte of double-
byte instruction) will be output from memory following
DFLG _ Set high only when second byte of Delay
Instruction is to be read from memory following NADS.
Execution of the Delay Instruction then starts at trailing
edge of NRDS. Upon completion, SC/MP provides NADS
output to initiate next input/output cycle if bus access
is granted. Time in microcycles from leading edge of
delay flag to leading edge of subsequent NADS output is
computed from the following formula:
Delay = [9 + 2(AC) + 2 disp + 29 disp] microcycles
(AC) = unsigned contents of accumulator
disp = unsigned displacement value contained in
second byte of Delay Instruction
The time derived from the above formula does not
include the four microcycles required to fetch the first
byte of the Delay Instruction. Thus, when the Delay
Instruction is used for software timing, total instruction further processing of Halt Instruction occurs. In
execution time equals [13 + 2(AC) + 2 disp + 29 disp] effect, this procedure ensures HFLG is output in
microcycles. advance of the next instruction to be fetched from
memory.
When Halt Instruction is executed, instruction HFLG - Set high only during addressing interval of read
decode and control logic inhibits incrementing of cycle that follows Halt Instruction. HFLG may be used
program counter for one input/output cycle. Thus, to cause user-provided external logic to set the CONT
Halt Instruction is read from memory a second input low, and thereby to effect a programmed halt.
time to enable generation of HFLG output, but no Since HFLG read cycle precedes the next instruction
" INITIATE INPUI/DUTPUT CYCLE
START lmsmucnom FETCH OR
MEMORY -REFERENCE
msmucnom EXECUTION)
CHECK NBREO LINE i/gt/IR/wi' Q15", NENIN Low
. 1 SEE NOTEI YES
SEE NOTE 1 -
BUSBIJSY EXECUTE DATA TRANSFER V
IADRESSUUTPUT F0LLOWE0 ,-K NEN|N=HIBH®
YES av READ nn WRITE)
NBREllLOW
uanzu ISPUlLED TO vcc
[NBREOSERVES AS seenots 2 " EXTERNAL
SETNBREO LOW OUTPUT FOR REMAINDER LOAD RESlSTUR
_ or l/D CYCLE)
A. NBREO and NENIN Processing Sequence
NENIN l (ii) l
I l I E5: ft-m, (NENIND
y I ill I 2 l
l I (F) I
To voautusr)-1 - -l 4-19 mmoun Cr)
1 F----------
NENOUT \ l(C4) ci/" l
[4-192 mos»
Mrs i? 32 l 'il/ll, R
nnnsmwns ///// ”'GHZ/ w"" w"'" ',, / rci'ir"" v,,cd
B. NBREO, NENIN, and NENOUT Timing
Note I: NENOUT is always high while SC/MP is actually using bus; that is. NENIN input and NBREO output are low.
Note 2: When SC/MP is not using bus (NBREO output or NENIN input high), NENOUT is held in same state as NENIN input.
Note 3: NENOUT goes low to indicate that SC/MP was granted access to bus (NENIN low) but is not using bus.
Note 4: NENOUT goes high in response to high NENIN input.
Nate 5: SC/MP generates bus request; bus access not granted because NENIN high.
Note 6: NENIN goes low. Bus access now granted and input/output cycle actually initiated. If NENIN is set high while SC/MP has access to
the bus, the address and data ports will go to the high-impedance (Tri-State"?) state, but NBREO will remain low, When NENIN is subsequently
set low, the input/output cycle will begin again.
Note 7: Input/output cycle completed. NENOUT goes low to indicate that SC/MP granted access to bus but not using bus, " NENIN had been
set high before completion of input/output cycle, NENOUT would have remained high.
FIGURE a. Bus Access Control
m oimrm-i----l
nsunur /i I N
l--- Tiowuos)--+s [ADS)>1 I
mos N' IN
---v l-Ts (ADDRI
AD'II-ADUO HIGH Z I I ADDRESS VALID A HIGH 2
/ I , /
rs(sTAT)-l _ -H |<-Tul / " /
[137-090 f" %IGHZ WI,,, (Atl"lffi'is / //HIGHZ 3:5?) //HIGH "zCcrCii';i
I --I I‘TDIRDS) l ----l H-mmn)
NRDS Wy'" HIG/HZ
"t, I 'v/""T"ri" /
T mm T(nn)
H-------: i,-------) "l
I-------!
Note: Timing is valid when NENIN is low before NBREO is set low by SC/MP; see figure 4 for NADS timing when NENIN is
set low after NBREO.
FIGURE 5. SCIMP Data Input Timing
MI I vc"'""
m tNimetl)-_
NENO UT I I N
l--- w/us)-----} Tw IADS)>|
-1 |4-15 (norm) I I
t , I I
(jiiift"f l , r,Ct'fA, 7
A01rA008 HIGH 1 ADDRESS VALID HIGH 2
(jiii'jCCy I l r,Cr"f, A
TssTAT)-l I--- --I |<-THISTA1) ->H<-1Huwnm
037 mm /fffr,t, 2 l Jgil'fR',s WRITE DATA VALID : HIGH 2
I l-rs--} _ H-n, (wn)
pr w/f,," r" I
was HIGH 2 men 2
Fe--- To films) ~I: = erw (qu1
FIGURE 6. Data Output Timing
fetch, termination of programmed halt enables fetch of
first instruction that follows Halt Instruction.
After resetting the NADS output, SC/MP generates an
NRDS or NWDS strobe, respectively, to initiate a data-
input (read) or data-output (write) operation. For a read
operation, input data are strobed into SC/MP from the
8-bit bus on the trailing edge of the NRDS strobe. For a
write operation, SC/MP places valid output data on the
8-bit bus on the leading edge of the NWDS strobe. After
resetting the NRDS or NWDS strobe to complete the
data transfer, SC/MP then resets the NBREO signal to
indicate that the system busses are free for use by
another controller.
INPUT/OUTPUT CYCLE EXTENSION
As shown in figure 7, the NHOLD signal may be set low
prior to the trailing edge of the NRDS or NWDS strobe
to cause SC/MP to lengthen the input/output cycle by
holding the strobe active until after the NHOLD signal
is returned high. Since there is no restriction on the
maximum duration of the NHOLD signal, it can be used
in a variety of applications ranging from accommodation
of memories/peripherals with long access times to single-
cycle control of the operating program for software
debug purposes.
Figure 8 illustrates a typical circuit that may be used to
generate an NHOLD signal of repeatable duration. The
circuit shown employs a DM74155 8-Bit Parallel ln/
Serial Out Shift Register to allow selection of an input/
output cycle extend time that ranges from Tc/2 to
2Tc in increments of Tc/2. Functional operation of the
circuit is controlled by the NADS strobe and XOUT
signals. Each time that the NADS strobe goes low, the
data present at the A through H terminals are loaded
into the shift register in parallel. When the NADS strobe
subsequently returns high, the data are then shifted out
serially on the positive-to-negative transitions of XOUT.
NEREH l
N0 EXTENSION OF INPUTIOUTPUT EVDLE
Thus, the NHOLD output of the circuit is set low on the
leading edge of each NADS strobe and, as shown in the
chart that accompanies the circuit diagram, it remains
low for a time period ranging from three clock cycles
minimum (B, C, D, and E inputs = Logic "I'') to seven
clock cycles maximum (B, C, D, and E inputs = Logic
It is important to note that instruction execution time
is increased whenever an input/output cycle is extended
via the NHOLD signal. For purposes of computing the
increase in instruction execution time, it is necessary to
distinguish between the terms Input/Output Cycle
Delay Period and lnput/Output Cycle Extend Time. The
term Input/Output Cycle Delay Period refers to the time
that the NRDS/NWDS strobe is actually "stretched" to
provide the required memory or peripheral access time.
The term lnput/Output Cycle Extend Time refers to the
additional number of microcycles required by the
internal SC/MP microprogram to complete the extended
input/output cycle; that is:
Input/Output Cycle
Extend Time
Input/Output Cycle
Delay Period
TC/2 through 2Tc (> 0 < 1 pcycle) 1 ucycle
5Tc/2 through 4TC (> 1 < 2 ucyclesl 2 ucycles
9TC/2 through 6TC (> 2 'C, 3 pcycles) 3 pcycles
etc. etc.
The total increase in instruction execution time, there-
fore, is equal to the Input/Output Cycle Extend Time
multiplied by the total number of input/output cycles
associated with the instruction. For example, a DLD
Instruction is normally executed in 22 microcycles.
Since this instruction employs three read input/output
cycles and one write input/outputcycle, an /nput/Output
Cycle Extend Time of one microcycle would increase
total DLD Instruction execution time to 26 microcycles.
NHOLD NHOLD CAN CHANGE /
NRDSINWDS
NBRED \
NHOLD NMDLD CAN CHANGE N
NRDS/NWDS N
I--rsounm--H
I"--- IslHOLU) _.| _
EXTENSION 0F INPUT/UUTPUT CYCLE
",,',i, NHDLD mm CHANGE
mtuntm I
'l---- tmmntni "I
/ , NHOL0 CAN CHANGE
tthmm I-------)----! TutHDlD)
lp- -----
=/ l' 7
Note1: In order to extend the input/output cycle, NHOLD must remain low until the paint where NRDS/NWDS would have madea
low-to-high transition with NHOLD inactive, Dashed line indicates the trailing edge of NRDS/NWDS when NHOLD is not active.
FIGURE 7. NHOLD Timing
INPUT/OUTPUT EVE
TIME SELECTI
LE EXTEND
4T] , , , =
A B [I D E
LOGIC "I'' SI ,
2 74165 so - NHOL0
xour _ >CLK (TO SUM?)
(FROM SC/MP) LOAD'
T 1 ls
NADS -
(FROM SEIMP) -
Data Inputs I NHOLD Duration Input/Output Cycle 39112:: lit,',':,'"
B C D E i (in clock cycles) Delay Period 'Extend Time [TACC (RDH
1 l In Microcycles
1 1 1 1 i: 3 f 0 0 2TC - 200
1 1 1 0 i 4 Tc/2 1 (5TC/2) - 200
1 1 0 0 i 5 TC I 1 3TC - 200
1 o 0 0 l 6 3Tc/2 i 1 (7TC/2) - 200
0 0 0 0 i 7 2Tc 1 i 4TC-200
FIGURE 8. Typical NHOLD Conttal Circuit
Serial Data Transfers
Serial input/output data transfers can be used efficiently
with very slow input/output peripherals such as X-Y
Plotters, teletypewriters, slow-speed printers, and so
forth. Such transfers can be effected in any of the
following manners:
1. By assigning serial input/output functions to the
extensuon register via the SIO (Serial lnput/Output)
instruction. When this instruction is executed, the
contents of the extension register are shifted right one
bit. At the same time, data present on the SIN line are
shifted into bit position 7 of the extension register and
the original contents of bit position 0 are shifted into a
flip-flop to provide a latched output of the SOUT line.
The SOUT data are then held latched until the next SIO
instruction is executed.
2. By using one of the status flags as an output data bit
and one of the sense lines as an input data bit.
3. By implementing external logic such that only one
line of the 8-bit data input/output bus is used.
For synchronous systems, serial data input/output timing
may be provided by program loops that employ the
delay instruction, or by using one or more of the transfer
instructions (see table 2) to test the output of an external
timing circuit. For asynchronous systems, one of the
sense inputs can be used for testing bit-received/ready
status and a pulsed flag output can be provided, under
program control, for peripheral indexing each time that
a data bit is actually shifted in or out.
Systems that have several input/output devices must be
multiplexed; device selection can then be accomplished
using the status flag outputs of SC/MP, or by using
parallel input/output commands to load an external
latch. Systems that do not require serial input/output
capability can employ the SIN and SOUT lines as a sense
input and flag output, respectively.
Interrupts
When the internal interrupt enable (IEI flag is set under
program control, the Sense A line is enabled to serve as
an interrupt request input; when the IE flag is reset,
SC/MP is inhibited from detecting interrupts. Thus,whi|e
the IE flag is set, the Sense A input is tested prior to the
fetch phase of each instruction as shown in figure 9.
Upon detection of an interrupt request (Sense A high),
the following events occur automatically.
1. The status register IE flag is reset to prevent SC/MP
from responding to any further interrupt requests.
Interrupt request capability can then be reenabled during
or at the end of the ensuing user-generated interrupt
service routine via the IEN (Enable Interrupt) Instruc-
tion or by copying the accumulator into the status
register.
2. The contents of the program counter are exchanged
with the contents of the pointer register 3.
3. The contents of the program counter are incremented
by one to address the first instruction of the user-
generated interrupt service routine.
The interrupt system must be armed before interrupts
are enabled. This is accomplished as follows:
l. First, the Interrupt Enable Bit in the Status Register
LS set true by executing either an Enable Interrupt
Instruction (IEN) or a Copy Accumulator to Status
Register instruction (CAS).
2. Second, one additional instruction is fetched and
executed.
A return from interrupt is accomplished by executing
two instructions: Enable Interrupt HEN] immediately
followed by Exchange Pointer 3 with Program Counter
(XPPC 3).
Microprocessor Halt
The CONT input to SC/MP is provided to enable
suspension of operation without loss of internal status.
Processing of the CONT input is shown in figure 9. Since
this is an asynchronous input, it can be controlled by
external timing logic, or as stated previously, the HALT
flag output that appears on the 8-bit data bus (during
the read cycle that follows execution of a Halt Instruc-
tion) can be used with an external circuit to effect a
programmed halt condition. Note that when an interrupt
request is detected while the CONT input is low, the first
instruction of the user-generated interrupt service routine
is automatically executed. Thus, the first instruction of
the interrupt service routine can be used to reset the
external CONT input logic and, thereby, to terminate
the microprocessor halt condition if so desired.
After execution of an instruction, the CONT input must
be high for a minimum time of 2Tc (1 microcycle) in
order to fetch and execute the next instruction.
INITIALIZE
ttt INTERRU" "
SYSTEM
RESET IMTEFIRUPT ENABLE
EXECUTE XPPCJ
INIERRUPT
INCREMENT PC
FETCH INSTRUCTION
EXECUTE lNSTRUCTION
FIGURE 9.
Microprocessor Halt and Interrupt Request Input Processing
Instruction Set
The SC/MP instruction set provides the genera|~purpose
user of microprocessors a powerful programming capa-
bility along with above-average flexibility and speed. The
instruction set consists of 46 instructions, which comprise
eight general categories. A listing of the complete
instruction set is provided in table 2; typical instruction
execution times are given in table 3, and notations and
symbols used as shorthand expressions of instruction
capability are defined in table 4.
ADDRESSING
During execution, instructions and data defined in a
program are stored into and loaded from specific
memory (ocations, the accumulator, or selected registers.
Because SC/MP, memory (read/write and read-onlyl,
and peripherals are on a common data bus, any instruty
tion used to address memory may be used to address the
peripherals. The formats of the instruction groups that
reference memory are shown below.
7,..,321,0‘7H ..... 0
oucode m mil nisp Memory FRefererecelnstrucUoris
h Memory Increment/Dememem
opcode p r mm instructions and Transfer ltistruciiuns
Memory-reference instructions use the PC-relative, irn-
dexed, or auto-indexed methods of addressing memory.
The memory-increment/decrement instructions and the
transfer instructions use the PC-relative or indexed
methods of addressing.
The various methods of addressing memory and peri-
pherals are shown below.
Immediate addressing is an addressing format specific to
the immediate instruction group.
Type of Operand Formats
Addressing m ptr disp
PC-relative 0 0 -128 to +127
Indexed 0 1,2, or3 -128 to +127
Immediate 1 0 -128 to +127
Auto-indexed 1 1, 2, or 3 -128 to +127
For PC-relative, indexed, and auto-indexed memory-
reference instructions, another feature of the addressing
architecture is that the contents of the extension register
are substituted for the displacement if the instruction
displacement equals -128(-X'80)_
All arithmetic operations associated with address
formation affect only the 12 lowrorder address
bits; no carry is provided to the 4 high-order bits,
For systems employing memories of 4k or less, the
high-order bits can be ignored as they are set to
0000 following initialization For systems employ-
ing larger memories, the highrorder bits must be
set to the starting address of the desired 4k block
of memory. For example:
00012enables memorylocationsUJ0016 - IFFF16
to be addressed.
00102 enables memory locations 200016 - 2FFF16
to be addressed and so forth.
PC-Relative Addressing - A PC-relative address is formed
by adding the displacement value specified in the operand
field of the instruction to the current contents of the
program counter. The displacement is an 8-bit twos-
complement number, so the range of the PC-relative
addressing format is 42810 to H2710 locations from
the current contents of the program counter.
Immediate Addressing - Immediate addressing uses the
value in the second byte of a double-byte instruction as
the operand for the operation to be performed (see
below}.
For example, compare a Load (LDI instruction to a Load
Immediate (LDI) instruction. The Load instruction uses
the contents of the second byte of the instruction in
computing the effective address of the data to be
loaded. The Load Immediate instruction uses the con-
tents of the second byte as the data to be loaded.
Indexed Addressing - Indexed addressing enables the
programmer to address any location in memory through
the use of the pointer register and the displacement.
When indexed addressing IS specified in an instruction,
the contents of the designated pointer register are added
to the displacement to form the effective address. The
contents of the pointer register are not modified by
indexed addressing.
Auto-lndexed Addressing - Auto-indexed addressing
provides the same capabilities as indexed addressing
along with the ability to increment or decrement the
designated pointer register by the value of the displace-
ment. If the displacement is less than zero, the pointer
register is decremented by the displacement before the
contents of the effective address are fetched or stored.
If the displacement is equal to or greater than zero, the
pointer register is used as the effective address, and the
pointer register is incremented by the displacement after
the contents of the effective address are fetched or
stored.
System Implementation
Figures 10 through 12 illustrate typical SC/MP system
configurations. In figure 10, SC/MP is shown intercom
nected to three memory devices to form a stand-alone
4-device system that provides 256 words of read/write
memory and 2,048 words for program storage. Figure 11
shows SC/MP interconnected to an external controller
for Direct Memory Access (DMA) operation, and figure
12 illustrates a multiprocessor application using SC/MP's
built-in1ogic to control bus access.
r xm xnut A 1
NBREI] NWDS Tr
mnas fir
‘sv “CC SEAM' I I 1 r
c--, £st cEtoaaNrcm - Ectzon R/W
nun nun ROM RAM
t "gm (IATA (M3143) ummruzssw mmm I(ISGN)
*Svt nunto PORT - '
cant nuunzss
NOTE PARTNuM8eRslutEStMlgm0br
SI _ . .' , mnmronmnou PURPOSES
INITIALIZE 0TH”! MEMORY CiWP0#ENTSWITti
"sl'lJl1c1, I . ll 1"l'll'Y CHARACTKHISTICSCN‘
o- //. f' /Aoua_éss/cou1 ’ t Y'" " -", - .', A
F _ , ',r
FIGURE 10. INS8060 Four-Chip System
PERIPHERA‘
“Rio - --, lt0UEST
ND CONVERTER
SC/MP WWW g IVA wwmnn.
nMn cnumuutn PERlPriERAtS mnusuucm, ETC.
usum - .-v PERIPHERAL
ENABLE
\ N s' " \
's,'-, 'x \73: t;
l, anoasss AND mutant pus ', .
J,'ii(ti,Ye?
Chin»? M&‘W Q12
.Y-\. JV,
30am nus jri's,
‘1 ohtl' Fl, “x
Ci? ',shi)ai.1c)i1,
KS. "13:15"
REID ONtY
MEMURV (RUM!
START lN'lJY/DUTPUT
READMRITE iAFTEroEtgitgiittEs Law)
MEMORY IREMI
CYCLE i
FIGURE 11.
INS8060 Interconnected fov Direct Memory Access (DMA) Operation
usnzm usnznz "REM
IENINI Immun - HEM"; usnoutz _ NENINn Ntluuvu -
SC/MP ttl SC/MP #2 SC/MP 'ttl
REA0 ONLY
MEMORY (ROW
REIDMRITE
MEMORY (RAM)
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FIGURE 12. Multiprocessor System Using SC/MP-H BuiIt-in Logic for Bus Control
TABLE 2. Bus Utilization of Each Instruction
INSTRUCTION
SCL. CCL. CSA, RR, RH L,
SR, SRL, and SIO
LDE, ANE, ORE, XRE,
CAS. IEN, and DINT
XAE, XPPC, and ADE
CAE, XPAH, and XPAL
JP, .12, and JNZ
(No jump)
JMP, JP, JZ. and JNZ
(Do jump)
LDI, ANI, om. and XRI
LO. AND. OR. XOR
DLD and ILD
DLY (minimum)
"r--"---------,'". IN MICROSECONDS ‘
0 , 2 3 4 5 6 7 8 9 10 11 12 t3 14 15 16 17 18 19 20 21 22 23 24 25 26
I I I I I I
I I I I I I I
I I I I I I I I
I I I I I I I I I LEGEND:
I I I I I I I I I I I I = BUS UTILIZATION INTERVAL
I 1 i FRSRKN I I l READ CYCLE WITH H-FLAG
O OUTPUT
I I El 1 I I sl l I l -OPERAND STORE
I I DI I I I (5:! I l I I I -BUS NOT RELEASED DURING
E 0 THISTIME
I I El I I I 31 I I I I I
I I [l I I I gI I I I I
I I “I I I I JI I I I I I I
I I I I I I I I I I I I I I I I
I I I I I IEI I I I I I I I I I I
I I I I I IgI I I I I I I I I I I I I
I I I I I I EI I I I I I I I SIF I I I I I
I I I I I I 'lt I I I I I I I §I$ I I I I I I
iititisT:iilillio')i'yiiiilillll
I I I I I I I I I I I I I I I I I I
I I I I I I I I I I I I I
0 1 2 3 4 5 6 7 a 9 IO 11 12 13 14 15 16 17 18 19 20 21 22 23 " 25 26
NS 10450
TABLE 3. SC/MP Instruction Summary
DOUBLE-BYTE INSTRUCTIONS
MNEMONIC DESCRIPTION OBJECT FORMAT OPERATION CYCLES
Memory Reference instructions 7 6 5 4 3 2 1 0 7 6 5 4 3 2 1 0
LD Load 1 100 OmIptr disp [ACP-(EA) 18
ST Store 1 1001 (EAH-iAC) 18
AND AND 1 1010 (ACH-IAC) AIEA1 18
OR OR 1 101 1 (ACH-IAC) V IEA) 18
XOR ExclusweOR 1 1 100 (ACP-(AClViEA) 18
DAD Decimal Add 1 1 1 01 (ACFFIACMQ +(EA110+1CY/L1:(CYIL) 23
ADD Add 1 1 1 10 (AcV-(AC)+(EA)r(CY/L);tcY/L),(OVl 19
CAD Cromplemerat and Add 1 1 1 1 1 1AC)“(AC) + ‘(EA1+1CY/L),1CY/L).10V) 20
Memory Increment/Decrement Instructions 7 6 5 4 3 2 1 017 6 5 4 3 2 1 01
ILD Increment and Load 101010 ptrl disp 1 (AC), (EA1-(EA) +1 22
OLD Decrement and Load 1011 10 (AC),(EAV (EA)- 1 22
Immediateinstructiuns 7 fi 5 4 3 21 0 7 6 5 4 3 2 10
LDI Load Immediate 1 10 0 010 0 data (ACH- data 10
ANI AND Immediate 1 1010100 (ACH 1AC)/\data 10
OR! OR Immedlate 1101 1100 (AC)-(AC)Vdata 10
XRi ExcluswerOR Immediate 1 1 1 001 0 o (AC)-(AC)Vdata 10
DAI Decunal Add Immediate 1 1 1 O1 10 o (AC). (ACHO ' dala10 +(CY/L)jCY/L) 15
ADI Add Immediate 1 1 1 1010 0 (AC)-(AC) + data +(CY/LlY/L),(OV) 11
CAI Commemem and Add Immediate 1 1 1 1 1 1 0 o (ACH (AC) + 'data ' (CY/LHCY/LHOV1 12
Transfer Instructions 7 6 5 4 3 21 017 6 5 4 3 21 0
JMP Jump 1001ooptrl dap [PCVVEA 11
JP Jump 11 Positive 100101 If (AC) 'e, 0, (PC)-EA 9,11
JZ Jumpd 2run 100110 lf(PC)--Ct(PC)-EA Sh11
JNZ Jump it Not Zero 10 01 1 1 |11AC11- 0,iPCl-EA 9,11
Double-Byte Miscellaneous Instructions 17 6 5 4 3 2 10 7 G 5 4 3 2 1 0
DLY Delay 110001 1 1 1 Jsp Count AC tcr-l, 13to
delay =13121ACH 2 disp 1 29 mp 131.593
mcrocycles
SINGLE-BYTE INSTRUCTIONS
MICRO-
MNEMONIC DESCRIPTION OBJECT FORMAT OPERATION CYCLES
Extensinn Register Instructions /6 5 4 3 2 1 0
LDE Load ACtrum Extensmn !01000000 (AC'r-(E) 6
XAE Exchange AC and Extunmon :0 0 0 0 0 0 Ol (AC)-(E! 7
ANE AND Extcnsmn 01010000 (AC)"(AC)/\1E1 6
ORE OR Extension '01011000 fAC)"(AC)\/1E1 6
XRE Excluswe-OR Extensuon 01 10 00 0 0 (AC). l/iCefiE) 6
DAE Dummdl Add Exlunsmn ',01 1010 0 0 (AC1'1AC110 +(E11011CY LHCY'LI 11
ADE Add Extenmon 01 1100 00 1AC)*1AC1*1E) '(CY'L),(CY/LL(OV) 7
CAE Complement and Add Exrcnsmn 01 1 1 10 00 (ACI. (AC1|‘(E1+1CY-LHCY'L),(OV) 8
Pointer Register Move instructions 7 5 5 4 3 2 1 0
XPAL Exchange Pomter Luv. 0 01 If) optr), (AC1-41PTR710) 8
XPAH Exchangu P0111101H1qh 0 D1 101 (ACl-(PTRis 8) 8
XPPC Exrhdnqne P01111111 wnh PC 0 01 1 1 1 (PCIHIPTR) 7
Shift.Rotate,Seriat I/O Instructions 75 5 4 3 2 1 0
510 Selldl Input Output .00011001 1150 '1E1.]1.51N‘1E7l, (E0)*SOUT 5
SR ShdtHift 100 011100 1AC.) '1AC. l). 0~~(Ac71 5
SRL Sltdtmghts.uth Lmk 00 01 1 101 (AC11"(AC1.1I. (CY‘L)"(AC7I 5
RR Rotate Rigm 00 O1 1 1 10 1AC;1"1AC111.1ACO)“(AC7) 5
RRL Hotate ngm mm Unk o 001 1 1 1 1 (ACl)-iACrrl,(ACiy "CY/Ll-l/kc) 5
Smgle-Byte Miscellaneous Instructions 7 6 5 4 3 2 1 0
HALT Halt 00000000 Pulse H-flaq 8
CCL ClearCarry Link 00000010 (CY/LV-O 5
SCL SetCarry Lunk 00000011 (CY/L)' 1 5
DINT Disable Interrupt 00000100 (IEP-O 6
IEN EnaMelmcuupt 00000101 11E1'1 6
(ISA Copy Status to AC 000001 10 (AC)- (SR1 5
CAS Copy AC to Status 0 0 0 0 01 1 1 (SRV (AC) 6
NOP No Operanon 0 0 0 010 0 0 None 5
TABLE A. Instruction Execution Time
READ WRITE TOTAL READ WRITE
INSTRUCTION CYCLES CYCLES MICROCYCLES INSTRUCTION CYCLES CYCLES MICROCYCLES
ADD 3 o 19 JP 2 o 9, 11 farJump
ADE 1 0 7 JZ 2 0 9,11 for Jump
ADI 2 O 11 LD 3 f) 18
AND 3 0 18 LDE 1 0 6
ANE 1 0 6 LDI 2 0 10
ANI 2 0 1O NOP 1 0 5
CAD 3 0 20 OR 3 0 18
CAE 1 0 8 ORE 1 0 6
CAI 2 0 12 CHI 2 0 10
CAS 1 0 6 RR 1 0 5
CCL 1 O 5 RRL 1 0 5
CSA 1 _ 0 5 SCL 1 0 5
DAD 3 1 o 23 s10 1 o 5
DAE 1 T o 11 SR 1 o 5
DAI 2 f o 15 SRL 1 o 5
DINT 1 I 0 6 ST 2 1 18
DLD 3 1 1 22 XAE 1 0 7
DLY 2 I 0 13- 131593 XOR 3 0 18
HALT 2 : 0 1 8 XPAH 1 0 8
IEN 1 E 0 ' 6 XPAL 1 0 8
ILD 3 r 1 1 22 XPPC 1 0 7
JMP 2 g 0 1 11 XRE 1 0 6
JNZ 2 0 i 9111013111111; XRI 2 0 10
Note If slow 111e111o1y 1911e111qused, the approprmtv delay shoultlloe adder! ior each road or wute cycle
TABLE B. Symbols and Notations Used to Express Instruction Execution
SYMBOL AND
NOTATION MEANING
AC 8-bit Accumulator.
CY/L Carry/Link Flag in the Status Register.
data Signed, 8-bit immediate data field.
disp Displacement; represents an operand in a nonmemory reference instruction or an address
modifier field in a memory reference instruction. It is a signed twos-complement number.
EA Effective Address as specified by the instruction.
E Extension Register; provides for temporary storage, variable displacements and separate serial
input/output port.
i Unspecified bit of a register.
IE Interrupt Enable Flag,
m Mode bit, used in memory reference instructions. Blank parameter sets m = o, @ sets m = 1.
0V Overflow Flag in the Status Register.
PC Program Counter (Pointer Register 0); during address formation, PC points to the last byte of
the instruction being executed.
ptr Pointer Register (ptr = 0 through 3). The register specified in byte 1 of the instruction.
ptrmm Pointer register bits; mm = 7 through'O or 15 through 8.
SIN Serial Input pin.
SOUT Serial Output pin.
SR 8-bit Status Register.
( ) Means "contents of." For example, (EA) is contents of Effective Address.
[ ] Means optional field in the assembler instruction format.
_ Ones complement of value to right of ""-.
- Means "replaces."
- Means "is replaced by.''
H Means "exchange."
© When used in the operand field of the instruction, sets the mode bit (m) to 1 for auto-
1ncrementing/auto-decrementing indexing.
10+ Modulo10 addition.
A AND operation.
V Inclusive-OR operation.
-V- Exclusive-OR operation.
2' Greater than or equal to.
= Equals.
i Does not equal.
INSBOBO- Single-Chip 8—Bit N-Channel Microprocessor (SC/MP Family)
Physical Dimensions
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NS Package Number N4OA
Ordering Information
The SC/MP device may be ordered through the local National Semiconductor sales representative or by contacting
our world or international headquarters listed below. The order numbers are as follows:
For an "N" package - INS8060N
For a "D'' package - INS80600
Mmmacvynj 41- P" me n "u rar''rreirrlcvrmg,rS mtenls 3081262 3189 b8, 3231797 3303356 33'767l. 3331071 338107r, $108542, MZIUES, 3426423, 3540698. 3515750, 35198W, 557431. 1560755.
356k" , 3571531 :5 Mry) 35 9659' 693069 35’1“}10 160 1169 3617359 'W. 313 353305?, 363813] 3643071 3651565 3693243
NIHoMI Semtetmductor Corporation
2900 Semmunduuor 0mm ganu Ciara Calulmma 950m [408; n: b000 TWA mm 139 9M0
N-Iionnl Semictmttuctor GmbH
BOB ruevslcnvuamuu Irr0ustrres0rtgste IO West Gerrndny Me \08141, 13,'1 we. 052w”
NS Eleclvonieo (MK) Ltd.
4 mm; m; Street Hm VIr-f)! szm Yong hnwtoon um“; Kong Tele 3-A1I2JI-B wag, 71866 Nhe HK m
NS 'ratematioetal Inc.
Mlyahe Bldg 6F 19 Yolsuvu Sronuhu m. Tnkyu mo Japan Tele 03.195 1711 m». Lissa;
NS Electronic: Ply. Ltd.
CNR Stwy Hugo l Muunum mam.» mywam vurma 1mg Ausuam Yple :11 7294:!” law: 430%
Nahona :32: not assume an mrswb‘ Cr rc! use ot 3M mnwlry tfesrrleC, no mcmt patent Memes ale :mulmd and Nahum vesevves the "tht. at any hme wwlhoul name, In mange 5m curcumy
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Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
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This file is the datasheet for the following electronic components:
INS8060D - product/ins8060d?HQS=T|-nu|I-null-dscatalog-df-pf-null-wwe
INS8060 - product/in38060?HQS=T|-nu|I-nulI-dscatalog-df—pf—nulI-wwe
INS8060N - product/in38060n?HQS=T|-nu|I-null-dscatalog-df—pf—nulI-wwe
