ICE3DS01LG ,Pulse Wide Modulation (PWM) control IC for fixed frequent (FF) operation modeDatasheet, V2.0, 15 May 2003PWM-FF ICICE3DS01LICE3DS01LGOff-Line SMPS Current Mode Controller with ..
ICE3PCS03G , Standalone Power Factor Correction (PFC) Controller in Continuous Conduction Mode (CCM)
ICL232 ,RS-232 Transceiver, 2T/2R, +5V, 120kbpsApplicationsICL232lPE -40 to 85 16 Ld PDIP E16.3• Any System Requiring RS-232 Communications Port- ..
ICL232CBE ,+5V Powered, Dual RS-232 Transmitter/ReceiverTMICL232June 2001 +5V Powered, Dual RS-232 Transmitter/Receiver
ICL232CBET , 5V Powered, Dual RS-232 Transmitter/Receiver
ICL232CBEZT , 5V Powered, Dual RS-232 Transmitter/Receiver
IDT71V424L10PHI , 3.3V CMOS STATIC RAM 4 MEG (512K x 8-BIT)
IDT71V424-L10PHI , 3.3V CMOS STATIC RAM 4 MEG (512K x 8-BIT)
IDT71V424L12PH , 3.3V CMOS STATIC RAM 4 MEG (512K x 8-BIT)
IDT71V424L12PHI , 3.3V CMOS STATIC RAM 4 MEG (512K x 8-BIT)
IDT71V424L15PH , 3.3V CMOS STATIC RAM 4 MEG (512K x 8-BIT)
IDT71V424L15PHGI , 3.3V CMOS STATIC RAM 4 MEG (512K x 8-BIT)
ICE3DS01L-ICE3DS01L .-ICE3DS01LG
Pulse Wide Modulation (PWM) control IC for fixed frequent (FF) operation mode
PWM-FF IC
ICE3DS01L
ICE3DS01LG
Off-Line SMPS Current Mode
Controller with integrated 500V
Startup Cell
For questions on technology, delivery and prices please contact the Infineon Technologies Offices in Germany or
the Infineon Technologies Companies and Representatives worldwide: see our webpage at http://
www.infineon.com
CoolMOS™, CoolSET™ are trademarks of Infineon Technologies AG.
ICE3DSO1L(G)
Revision History: 2003-05-15 Datasheet
Previous Version:
F3
ICE3DS01L
ICE3DS01LG
Off-Line SMPS Current Mode Controller
with integrated 500V Startup Cell
Product HighlightsActive Burst Mode to reach the lowest
Standby Power Requirements < 100mWLatched Off Mode to increase Robustness
and Safety of the SystemAdjustable Blanking Window for High Load
Jumps to increase Reliability
FeaturesActive Burst Mode for lowest Standby Power
@ light load controlled by Feedback SignalFast Load Jump Response in Active Burst Mode500V Startup Cell switched off after Start Up110kHz internally fixed Switching FrequencyLatched Off Mode for Overtemperature DetectionLatched Off Mode for Overvoltage DetectionLatched Off Mode for Short Winding DetectionAuto Restart Mode for Overload and Open LoopAuto Restart Mode for VCC Undervoltage User defined Soft Start Minimum of external Components requiredMax Duty Cycle 72% Overall Tolerance of Current Limiting < ±5%Internal Leading Edge BlankingSoft Switching for Low EMI
DescriptionThe F3 Controller provides Active Burst Mode to reach the
lowest Standby Power Requirements <100mW at no load.
As during Active Burst Mode the controller is always active
there is an immediate response on load jumps possible
without any black out in the SMPS. In Active Burst Mode
the ripple of the output voltage can be reduced <1%.
Furthermore Latched Off Mode is entered in case of
Overtemperature, Overvoltage or Short Winding. If
Latched Off Mode is entered only the disconnection from
the main line can reset the Controller. Auto Restart Mode
is entered in case of failure modes like open loop or
overload. By means of the internal precise peak current
limitation the dimension of the transformer and the
secondary diode can be lower which leads to more cost
efficiency. An adjustable blanking window prevents the IC
from entering Auto Restart Mode or Active Burst Mode in
case of high Load Jumps.
Table of ContentsPagePin Configuration and Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51.1Pin Configuration with P-DIP-8-6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.2Pin Configuration with P-DSO-8-8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .5
1.3Pin Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6
Representative Blockdiagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7
Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .83.1Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.2Power Management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8
3.3Startup Phase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9
3.4PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.4.1Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.4.2PWM-Latch FF1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.4.3Gate Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10
3.5Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.5.1Leading Edge Blanking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.5.2Propagation Delay Compensation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11
3.6Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.6.1Adjustable Blanking Window . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12
3.6.2Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.6.2.1Entering Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.6.2.2Working in Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.6.2.3Leaving Active Burst Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13
3.6.3Protection Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.6.3.1Latched Off Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14
3.6.3.2Auto Restart Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .164.1Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.2Operating Range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16
4.3Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.3.1Supply Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.3.2Internal Voltage Reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17
4.3.3PWM Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.3.4Control Unit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18
4.3.5Current Limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
4.3.6Driver Section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19
Typical Performance Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . .20
Pin Configuration and Functionality1.1Pin Configuration with P-DIP-8-6Figure 1Pin Configuration P-DIP-8-6(top view)
Note:Pin 4 and 5 are shorted within the DIP
package.
1.2Pin Configuration with P-DSO-8-8Figure 2Pin Configuration P-DSO-8-8(top view)
1.3Pin Functionality
SoftS (Soft Start & Auto Restart Control)The SoftS pin combines the function of Soft Start in
case of Start Up and Auto Restart Mode and the
controlling of the Auto Restart Mode in case of error
detection. Furthermore the blanking window for high
load jumps is adjusted by means of the external
capacitor connected to SoftS.
FB (Feedback)The information about the regulation is provided by the
FB Pin to the internal Protection Unit and to the internal
PWM-Comparator to control the duty cycle. The FB-
Signal controls in case of light load the Active Burst
Mode of the controller.
CS (Current Sense)The Current Sense pin senses the voltage developed
on the series resistor inserted in the source of the
external PowerMOS. If CS reaches the internal
threshold of the Current Limit Comparator, the Driver
output is immediately switched off. Furthermore the
current information is provided for the PWM-
Comparator to realize the Current Mode.
GateThe Gate pin is the output of the internal driver stage
connected to the Gate of an external PowerMOS.
HV (High Voltage)The HV pin is connected to the rectified DC input
voltage. It is the input for the integrated 500V Startup
Cell.
VCC (Power supply)The VCC pin is the positive supply of the IC. The
operating range is between 8.5V and 21V.
GND (Ground)The GND pin is the ground of the controller.
Representative Blockdiagram
Functional DescriptionAll values which are used in the functional description
are typical values. For calculating the worst cases the
min/max values which can be found in section 4
Electrical Characteristics have to be considered.
3.1Introduction
The F3 is the further development of the F2 to meet the
requirements for the lowest Standby Power at
minimum load and no load conditions. A new fully
integrated Standby Power concept is implemented into
the IC in order to keep the application design easy.
Compared to F2 no further external parts are needed to
achieve the lowest Standby Power. An intelligent
Active Burst Mode is used for this Standby Mode. After
entering this mode there is still a full control of the
power conversion by the secondary side via the same
optocoupler that is used for the normal PWM control.
The response on load jumps is optimized. The voltage
ripple on Vout is minimized. Vout is further on well
controlled in this mode.
The usually external connected RC-filter in the
feedback line after the optocoupler is integrated in the
IC to reduce the external part count.
Furthermore a high voltage startup cell is integrated
into the IC which is switched off once the Undervoltage
Lockout on-threshold of 15V is exceeded. The external
startup resistor is no longer necessary. Power losses
are therefore reduced. This increases the efficiency
under light load conditions dramatically.
The Soft-Start capacitor is also used for providing an
adjustable blanking window for high load jumps. During
this time window the overload detection is disabled.
With this concept no further external components are
necessary to adjust the blanking window.
A new Latched Off Mode is implemented into the IC in
order to increase the robustness and safety of the
system. Latched Off Mode is only entered if very
dangerous conditions occur that damage the SMPS if
not switched off immediately. A restart of the system
can then only be done by disconnecting the AC line.
Auto Restart Mode reduces the average power
conversion to a minimum. In this mode malfunctions
are covered that could lead to a destruction of the
SMPS if no dramatically reduced power limitation is
provided over time. Once the malfunction is removed
normal operation is immediately started after the next
Start Up Phase.
The internal precise peak current limitation reduces the
costs for the transformer and the secondary diode. The
SMPS. There is no need for an extra over sizing of the
SMPS, e.g. the transformer or PowerMOS.
3.2Power Management
Figure 4Power Management
The Undervoltage Lockout monitors the external
supply voltage VVCC. When the SMPS is plugged to the
main line the internal Startup Cell is biased and starts
to charge the external capacitor CVCC which is
connected to the VCC pin. The VCC charge current
that is provided by the Startup Cell from the HV pin is
1.05mA. When VVCC exceeds the on-threshold
VCCon=15V the internal voltage reference and bias
circuit are switched on. Then the Startup Cell is
switched off by the Undervoltage Lockout and therefore
controller can only take place after Active Mode was
entered and VVCC falls below 8.5V.
The maximum current consumption before the
controller is activated is about 170µA.
When VVCC falls below the off-threshold VCCoff=8.5V the
internal reference is switched off and the Power Down
reset let T1 discharging the soft-start capacitor CSoftS at
pin SoftS. Thus it is ensured that at every startup cycle
the voltage ramp at pin SoftS starts at zero.
The internal Voltage Reference is switched off if
Latched Off Mode or Auto Restart Mode is entered.
The current consumption is then reduced to 300µA.
When Active Burst Mode is entered the internal Bias is
switched off in order to reduce the current consumption
below 1.1mA while keeping the Voltage Reference still
active as this is necessary in this mode.
In case Latched Off Mode is entered VCC needs to be
lowered below 6V to reset the Latched Off Mode. This
is done usually by disconnecting the SMPS from the
AC line.
3.3Startup Phase
capacitor CSofts in combination with the internal pull up
resistor RSoftS determines the duty cycle until VSoftS
exceeds 4V.
In the beginning CSoftS is immediately charged up to
approx. 1V by T2. Therefore the Soft Start Phase takes
place between 1V and 4V. Above VSoftsS = 4V there is
no longer duty cycle limitation DCmax is controlled by
comparator C7 as comparator C2 blocks the gate G7
(see Figure 6).The maximum charge current in the very
first phase when VSoftS is below 1V is limited to 1.9mA.
Figure 6Startup Phase
By means of this extra charge stage there is no delay
in the beginning of the Startup Phase when there is still
no switching. Furthermore Soft Start is finished at 4V to
have faster the maximum power capability. The duty
cycles DC1 and DC2 are depending on the mains and
the primary inductance of the transformer. The
limitation of the primary current by DC2 is related to
VSoftS = 4V. But DC1 is related to a maximum primary
current which is limited by the internal Current Limiting
with CS = 1V. Therefore the maximum Startup Phase
is divided into a Soft Start Phase until t1 and a phase
from t1 until t2 where maximum power is provided if
demanded by the FB signal.
3.4PWM Section
Figure 7PWM Section
3.4.1Oscillator
The oscillator generates a frequency fswitch = 110kHz. A
resistor, a capacitor and a current source and current
sink which determine the frequency are integrated. The
charging and discharging current of the implemented
oscillator capacitor are internally trimmed, in order to
achieve a very accurate switching frequency. The ratio
of controlled charge to discharge current is adjusted to
reach a maximum duty cycle limitation of Dmax=0.72.
3.4.2PWM-Latch FF1
The oscillator clock output provides a set pulse to the
PWM-Latch when initiating the external Power Switch
conduction. After setting the PWM-Latch can be reset
by the PWM comparator, the Soft Start comparator, the
Current-Limit comparator or comparator C3. In case of
resetting the driver is shut down immediately.
3.4.3Gate Driver
The Gate Driver is a fast totem pole gate drive which is
designed to avoid cross conduction currents and which
is equipped with a zener diode Z1 (see Figure 8) in
Figure 8Gate Driver
The driver-stage is optimized to minimize EMI and to
provide high circuit efficiency. This is done by reducing
the switch on slope when exceeding the external
Power Switch threshold. This is achieved by a slope
control of the rising edge at the driver’s output (see
Figure 9).
Figure 9Gate Rising Slope
Thus the leading switch on spike is minimized. When
the external Power Switch is switched off, the falling
shape of the driver is slowed down when reaching 2V
to prevent an overshoot below ground. Furthermore the
driver circuit is designed to eliminate cross conduction
of the output stage.
VCC
PWM-Latch
Gate
3.5Current Limiting
Figure 10Current Limiting
There is a cycle by cycle Current Limiting realized by
the Current-Limit comparator C10 to provide an
overcurrent detection. The source current of the
external Power Switch is sensed via an external sense
resistor RSense . By means of RSense the source current
is transformed to a sense voltage VSense which is fed
into the pin CS. If the voltage VSense exceeds the
internal threshold voltage Vcsth the comparator C10
immediately turns off the gate drive by resetting the
PWM Latch FF1. A Propagation Delay Compensation
is added to support the immediate shut down without
delay of the Power Switch in case of Current Limiting.
The influence of the AC input voltage on the maximum
output power can thereby be avoided.
To prevent the Current Limiting from distortions caused
by leading edge spikes a Leading Edge Blanking is
integrated in the current sense path for the
comparators C10, C12 and the PWM-OP.
A further comparator C11 is implemented to detect
dangerous current levels which could occur if there is a
short winding in the transformer or the secondary diode
is shorten. To ensure that there is no accidentally
The output of comparator C12 is activated by the Gate
G10 if Active Burst Mode is entered. Once activated the
current limiting is thereby reduced to 0.257V. This
voltage level determines the power level when the
Active Burst Mode is left if there is a higher power
demand.
3.5.1Leading Edge Blanking
Figure 11Leading Edge Blanking
Each time when the external Power Switch is switched
on a leading edge spike is generated due to the
primary-side capacitances and secondary-side rectifier
reverse recovery time. To avoid a premature
termination of the switching pulse this spike is blanked
out with a time constant of tLEB = 220ns. During that
time there can’t be an accidentally switch off of the gate
drive.
3.5.2Propagation Delay Compensation
In case of overcurrent detection the shut down of the
external Power Switch is delayed due to the
propagation delay of the circuit. This delay causes an
overshoot of the peak current Ipeak which depends on
the ratio of dI/dt of the peak current (see Figure 12).
Figure 12Current Limiting
the overshoot dependency on dI/dt of the rising primary
current. That means the propagation delay time
between exceeding the current sense threshold Vcsth
and the switch off of the external Power Switch is
compensated over temperature within a wide range.
Current Limiting is now possible in a very accurate way
(see Figure 13).
E.g. Ipeak = 0.5A with RSense = 2. Without Propagation
Delay Compensation the current sense threshold is set
to a static voltage level Vcsth=1V. A current ramp of
dI/dt = 0.4A/µs, that means dVSense/dt = 0.8V/µs, and a propagation delay time of i.e. tPropagation Delay =180ns
leads then to an Ipeak overshoot of 12%. By means of
propagation delay compensation the overshoot is only
about 2% (see Figure 13).
Figure 13Overcurrent Shutdown
The Propagation Delay Compensation is realized by
means of a dynamic threshold voltage Vcsth (see Figure
14). In case of a steeper slope the switch off of the
driver is earlier to compensate the delay.
3.6Control Unit
The Control Unit contains the functions for Active Burst
Mode, Auto Restart Mode and Latched Off Mode. The
Active Burst Mode and the Auto Restart Mode are
combined with an Adjustable Blanking Window which is
depending on the external Soft Start capacitor. By
means of this Adjustable Blanking Window an
accidentally entering of the Active Burst Mode is
avoided. Furthermore the overload detection can be
deactivated for a certain time.
3.6.1Adjustable Blanking Window
Figure 15Adjustable Blanking Window
VSoftS is clamped at 4.4V by the closed switch S1 after
the SMPS is settled. If overload occurs VFB is
exceeding 4.8V. Auto Restart Mode can’t be entered as
G5 and G6 once VSofts has exceeded 5.4V. Therefore
there is no entering of Auto Restart Mode possible
during this charging time of the external capacitor
CSoftS. The same procedure happens to the external
Soft Start capacitor if a low load condition is detected
by comparator C6 when VFB is falling below 1.32V.
Only after VSoftS has exceeded 5.4V and VFB is still
below 1.32V Active Burst Mode is entered. Once Active
Burst Mode is entered gate G4 is blocked to ensure
that the blanking window is only active before entering
the Active Burst Mode.
3.6.2Active Burst Mode
The controller provides Active Burst Mode for low load
conditions at VOUT. Active Burst Mode increases
significantly the efficiency at light load conditions while
supporting a low ripple on VOUT and fast response on
load jumps. During Active Burst Mode which is
controlled only by the FB signal the IC is always active
and can therefore immediately response on fast
changes at the FB signal. The Startup Cell is kept
switched off to avoid increased power losses for the
self supply.
The Active Burst Mode is located in the Control Unit.
Figure 16 shows the related components.
3.6.2.1Entering Active Burst Mode
The FB signal is always observed by the comparator
C6 if the voltage level falls below 1.32V. In that case the
switch S1 is released which allows the capacitor CSoftS
to be charged starting from the clamped voltage level
at 4.4V in normal operating mode. The gate G11 is
blocked before entering Active Burst Mode. If VSoftS
exceeds 5.4V the comparator C3 releases the gate G6
to enter the Active Burst Mode. The time window that is
generated by combining the FB and SoftS signals with
gate G6 avoids a sudden entering of the Active Burst
Mode due to large load jumps. This time window can be
adjusted by the external capacitor CSoftS.
After entering Active Burst Mode a burst flag is set
which blocks the gate G4 and the internal bias is
switched off in order to reduce the current consumption
of the IC down to ca. 1.1mA. In this Off State Phase the
IC is no longer self supplied so that therefore CVCC has
to provide the VCC current (see Figure 17).
Furthermore gate G11 is then released to start the next
burst cycle once 1.32V is again exceeded.
It has to be ensured by the application that the VCC
remains above the Undervoltage Lockout Level of 8.5V
to avoid that the Startup Cell is accidentally switched
on. Otherwise power losses are significantly increased.
The minimum VCC level during Active Burst Mode is
depending on the load conditions and the application.
The lowest VCC level is reached at no load conditions
at VOUT.
3.6.2.2Working in Active Burst Mode
After entering the Active Burst Mode the FB voltage
rises as VOUT starts to decrease due to the inactive
PWM section. Comparator C5 observes the FB signal
if the voltage level 4V is exceeded. In that case the
internal circuit is again activated by the internal Bias to
start with switching. As now in Active Burst Mode the
gate G10 is released the current limit is only 0.257V to
reduce the conduction losses and to avoid audible
noise. If the load at VOUT is still below the starting level
for the Active Burst Mode the FB signal decreases
down to 1.32V. At this level C6 deactivates again the
internal circuit by switching off the internal Bias. The
gate G11 is released as after entering Active Burst
Mode the burst flag is set. If working in Active Burst
Mode the FB voltage is changing like a saw tooth
between 1.32V and 4V (see figure 17).
3.6.2.3Leaving Active Burst Mode
The FB voltage immediately increases if there is a high
blocks C12 by the gate G10. Maximum current can now
be provided to stabilize VOUT.
3.6.3Protection Modes
The IC provides several protection features which are
separated into two categories. Some enter Latched Off
Mode, the others enter Auto Restart Mode. The
Latched Off Mode can only be reset if VCC is falling
below 6V. Both modes prevent the SMPS from
destructive states. The following table shows the
relationship between possible system failures and the
chosen protection modes.
3.6.3.1Latched Off Mode
