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ICE1QS01G
Power Control ICs
ICE 1QS01
Controller for Quasiresonant
Switch Mode Power Supplies
Supporting Low Power Standby
and Power Factor Correction
Preliminary Data SheetICE1QS01
Controller for Switch Mode Power Supplies
Supporting Low Power Standby and
Power Factor Correction (PFC)
FeaturesLine Current Consumption with PFCStandby Input Power < 1 WStable Standby FrequencyLow Power ConsumptionVery Low Start-up CurrentSoft-Start for noiseless Start-upStandby Burst Mode with and without Control Signal for lowered Output
VoltagesDigital Frequency Reduction in small Steps at Decreasing LoadOver- and Undervoltage LockoutSwitch Off at Mains UndervoltageMains Voltage Dependent Fold Back Point CorrectionRinging Suppression Time Controlled from Output VoltageEasy Design InFree usable Fault Comparator
Functional DescriptionThe ICE1QS01 is optimized to control free running flyback converters with and without Power Factor Correction
(with PFC Charge Pump).
The switching frequency is reduced in small steps with decreasing load towards a minimum of 20kHz in
standby mode. This function is performed by a digital circuit to avoid any jitter also with periodically pulsed
loads. To provide extremely low power consumption at light loads, this device can be switched into Standby
Burst Mode. This is also possible without standby control signal (for adapter application).
Additionally, the start up current is very low. To avoid switching stresses of the power devices, the power
transistor is always switched on at minimum voltage. The device has several protection functions: VCC over-
and undervoltage, mains undervoltage and current limiting. Regulation can be done by using the internal error
amplifier or an opto coupler feedback. The output driver is ideally suited for driving a power MOSFET.
The ICE1QS01 is suited for TV-sets, VCR- sets, SAT- receivers and other consumer applications in the power range from 0 to app. 300 W.
Preliminary Data SheetICE1QS01
Block Diagram
Preliminary Data SheetICE1QS01
Pinning
Pin Configuration (top view)
Preliminary Data SheetICE1QS01
Functional Description
Start upAn internal start up diode is connected between pin PCS and pin VCC. Start up current is provided
via this diode if VPCS is higher than VCC + VBE (VBE = Base-Emitter-Voltage).
During start up the internal reference of the IC is shut off and current consumption is about 50uA.
There is only the start up circuitry working which determines the VCCon threshold. Gate driver OUT
is switched to low. An active shut down circuitry ensures that OUT is held below the MOS gate
threshold when the IC is in start up mode.
Block Diagram: Start Up
Preliminary Data SheetICE1QS01
Soft startThe internal reference of the IC is switched on when VCC exceeds the VCCon threshold. The IC
begins to work with soft start mode. Soft start is realized with an internal soft start resistor, an inter-
nal current sink, a current source and the external feedback capacitor connected at pin SRC. The
internal resistor is connected between the internal voltage reference and pin SRC. The current sink
is connected between pin SRC and GND. The value of the current is set with a timer. Immediately
after the IC is switched on the capacitor CSRC is charged with a current source up to 2.5V. This cur-
rent source is switched off 12 µsec after beginning of soft start. The current value of the current sink
is set with a timer. Every three msec the current of the current sink is reduced and so VSRC can
increase stepwise. The soft start is finished 24 msec after the IC is switched on. At the end of the
soft start the current sink is switched off.
Figure: Soft Start
PCS (Primary Current Simulation)A voltage proportional to the current of the power transistor is generated at Pin PCS by the RC-com-
bination R2, C2. The voltage at Pin PCS is forced to 1.5V when the power transistor is switched off
and during its switch on time C2 is charged by R2 from the rectified mains. The relation of VPCS and
Preliminary Data SheetICE1QS01the current in the power transistor (Iprimary) is:
Lprimary: Primary inductance of the transformer
The advantage of primary current simulation is the elimination of the leading edge spike, which is
generated when the power transistor is switched on.
RZI (zero crossing input and primary regulation)
Zero current counterEvery time when the falling voltage ramp of VRZI crosses the 25 mV threshold a pulse is sent to the
zero-current-counter and increases the counter by one. If zero-current-counter and up-down-coun-
ter are equal the gate drive OUT is switched to high. Up-down counter is influenced via SRC voltage
as described below. If VRZI is greater than 25 mV gate drive OUT is always switched low.
Figure: Zero crossing switching behaviourVPCS15V,LprimaryIprimary×C2×--------------------------------------------------------+=
Preliminary Data SheetICE1QS01
Ringing suppressionWhen VPCS reaches the feedback voltage VSRC the gate drive OUT is set to low and the ringing
suppression timer is started. This timer ensures that the gate drive cannot be switched on until this
ringing suppression time is passed. Duration of ringing suppression time depends on the VRZI volt-
age. Suppression time is 3 µsec if VRZI > 1V and it is 30 µsec if VRZI < 1V.
Figure: Ringing Suppression
Preliminary Data SheetICE1QS01
Primary regulationPrimary regulation is achieved by activating the internal current sink. The current sink is connected
between pin SRC and ground. If VRZI exceeds the 5V threshold the current sink is switched on. It is
switched off when VRZI falls below 5V. The current sink discharges the CSRC capacitor. CSRC is
charged via the internal 20k resistor. If VRZI exceeds the 4.4V threshold a flip-flop is set and the
resistor is switched off when VRZI falls below 50 mV. The resistor is switched on again with the fall-
ing slope of gate drive OUT.
Diagram Primary Regulation
Preliminary Data SheetICE1QS01
SRC (Regulation and soft start capacitor)The feedback capacitor is connected to pin SRC. The feedback voltage VSRC has two main func-
tions.
Function I (MOS FET on time): VSRC provides the switch off reference voltage. If VPCS (which con-
tains the primary current information) exceeds the VSRC voltage the external MOS transistor is
switched off.
Function II (MOS FET off time for frequency reduction): At low load the frequency is reduced by
ignoring zero crossing signals after the transformer demagnetization. VSRC determines the action of
the 4-bit up-down-counter which contains the number of zero crossings to be ignored. The content
of the up-down-counter is compared with the number of zero-current crossings of VRZI. If the
number of zero-current crossings in each period after the transformer demagnetization is equal to
the up-down-counter content the MOS is switched on. At low load conditions when VSRC is below
3.5V the counter is increased by one every 50 msec. The result is that the MOS transistor off-time
increases and duty cycle decreases. At high load conditions when VSRC is higher than 4.4V the
counter content is reduced by one every 50msec. So MOS transistor off-time will be reduced. With
this off-time regulation switching jitter can be eliminated.
The up-down-counter is immediately set to 0001 if a load jump occurs and VSRC exceeds 4.8 V.
This ensures that full power can be provided instantaneously.
The following table shows the SRC voltage range and the corresponding up-down counter action.
The information provided by VSRC is stored in two independent flip flops. An internal timer creates a
trigger pulse with a period of 50 msec. Every time the pulse occures the up-down counter checks
the status flip flops and acts depending on the flip flop information. After this pulse the flip flops are
reset. So change of voltage range is noticed by the logic only once during the 50 ms period. In the
diagram below the behaviour of the up-down counter is depicted in more detail.
