HYB39S512400AT-7.5 Fast Delivery |IC PHOENIX CO.,LIMITED

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HYB39S512400AT-7.5
SDRAM Components

All Rights Reserved.
Attention please!
The information herein is given to describe certain components and shall not be considered as a guarantee of
characteristics.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding
circuits, descriptions and charts stated herein.
Information
For further information on technology, delivery terms and conditions and prices please contact your nearest
Infineon Technologies Office (www.infineon.com).

HYB 39S512[40/80/16]0AT(L)
Revision History:Rev. 1.32004-03
Previous Version:Rev. 1.222003-09
1Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
1.2Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.1Signal Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.2Package P-TSOPII-54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.3Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12FunctionalDescription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1Operation Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.1Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5.1Read and write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5.2DQM Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5.3Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5.4Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20ElectricalCharacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.1Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.2AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Table1Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Table2Ordering Information. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table3Signal Pin Description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Table4Truth Table: Operation Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Table5Burst Length and Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table6Bank Selection by Address Bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Table7Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table8Input and Output Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Table9DC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table10IDD Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table11IDD Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Table12AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure1PinoutP-TSOPII-54. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure2Block Diagram for 128M×4 SDRAM ( 13 / 12 / 2 addressing) . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Figure3Block Diagram for 64M×8 SDRAM ( 13 / 11 / 2 addressing). . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
Figure4Block Diagram for 32M×16 SDRAM ( 13 / 10 / 2 addressing). . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure5Measurement conditions for tAC and tOH. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure6Package Outlines P-TSOPII-54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
List of Figures
OverviewOverview
1.1FeaturesFully Synchronous to Positive Clock Edge
0 to 70°C operating temperatureFour Banks controlled by BA0 & BA1Programmable CAS Latency: 2 & 3Programmable Wrap Sequence: Sequential or InterleaveProgrammable Burst Length: 1, 2, 4, 8 and full pageMultiple Burst Read with Single Write OperationAutomatic and Controlled Precharge CommandData Mask for Read / Write control (×4, ×8)Data Mask for byte control (×16)Auto Refresh (CBR) and Self RefreshPower Down and Clock Suspend Mode8192 refresh cycles / 64 ms (7,8 µs)Random Column Address every CLK ( 1-N Rule)Single 3.3V±0.3V Power SupplyLVTTL Interface versionsPlastic Packages:
P-TSOPII-54 400mil width (x4, x8, x16)
1.2Description
The HYB 39S512[40/80/16]0AT(L) are four bank Synchronous DRAM’s organized as 4 banks×32MBit ×4, 4
banks×16MBit ×8 and 4 banks×8Mbit ×16 respectively. These synchronous devices achieve high speed data
transfer rates for CAS-latencies by employing a chip architecture that prefetches multiple bits and then
synchronizes the output data to a system clock. The chip is fabricated with INFINEON’s advanced 0.14µm
512MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically
and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge
of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur at higher rate
than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst length,
CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operates with a single 3.3V±0.3V
power supply. All 512Mbit components are housed in P-TSOPII-54 packages.
Table1Performance
Part Number Speed Code
Speed Grade
max. Clock Frequency
Overview
Table2Ordering Information
Type
HYB
HYB
HYB
HYB
HYB
HYB
HYB
HYB
HYB
HYB
Pin ConfigurationPin Configuration
2.1Signal Pin Description
Table3Signal Pin Description
RAS
A0 - A12
BA0, BA1
DQx
Pin Configuration
2.2Package P-TSOPII-54
Table3Signal Pin Description
Pin
Pin Configuration
2.3Block Diagrams
Figure2Block Diagram for 128M×4 SDRAM ( 13 / 12 / 2 addressing)
Pin Configuration
Figure3Block Diagram for 64M×8 SDRAM ( 13 / 11 / 2 addressing)
Pin Configuration
Figure4Block Diagram for 32M×16 SDRAM ( 13 / 10 / 2 addressing)

Partno	Mfg	Dc	Qty	Available	Descript
HYB39S512400AT-7.5 \|HYB39S512400AT75	HY	N/a	13	avai	SDRAM Components