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Partno	Mfg	Dc	Qty	Available	Descript
HYB39S256800DT-7.5 \|HYB39S256800DT75	INFINEON	N/a	1500	avai	256-MBit Synchronous DRAM

HYB39S256800DT-7.5 ,256-MBit Synchronous DRAM
HYB39S512160AE-7.5 , 512-Mbit Synchronous DRAM
HYB39S512400AT-7.5 ,SDRAM ComponentsData Sheet, Rev. 1.3, March 2003HYB39S512400AT(L)HYB39S512800AT(L)HYB39S512160AT(L) 512-Mbit Synch ..
HYB39S64160BT-8 ,64M SDRAM ComponentHYB 39S64400/800/160BT(L)64-MBit Synchronous DRAM64-MBit Synchronous DRAM• High Performance: • Mult ..
HYB39S64160BT-8 ,64M SDRAM ComponentHYB 39S64400/800/160BT(L)64-MBit Synchronous DRAM64-MBit Synchronous DRAM• High Performance: • Mult ..
HYB39S64800AT-8 , 64 MBit Synchronous DRAM
ICS9LPRS511EGLF , Low Power Programmable Timing Control Hub™ for P4™ processor
ICS9LPRS511EGLF , Low Power Programmable Timing Control Hub™ for P4™ processor
ICS9UMS9610CKLFT , PC MAIN CLOCK
ICSLV810FILFT , Buffer/Clock Driver
ICT49FCT3805ASO , 3.3V CMOS BUFFER/CLOCK DRIVER
ICTE-18 ,Diode TVS Single Uni-Dir 18V 1.5KW 2-Pin Case 41A-04 Boxapplications0.210 (5.3) • High temperature soldering guaranteed:O0.190 (4.8) 265 C/10 seconds, 0.37 ..

HYB39S256800DT-7.5
256 MBit Synchronous DRAM
INFINEONTechnologies12002-04-23
256MBitSynchronousDRAM
TheHYB39S256400/800/160DT(L)arefourbankSynchronousDRAM’sorganizedas4banksx
16MBitx4,4banksx8MBitx8and4banksx4Mbitx16respectively.Thesesynchronousdevices
achievehighspeeddatatransferratesforCAS-latenciesbyemployingachiparchitecturethat
prefetchesmultiplebitsandthensynchronizestheoutputdatatoasystemclock.Thechipis
fabricatedwithINFINEON’sadvanced0.14µm256MBitDRAMprocesstechnology.
ThedeviceisdesignedtocomplywithallindustrystandardssetforsynchronousDRAMproducts,
bothelectricallyandmechanically.Allofthecontrol,address,datainputandoutputcircuitsare
synchronizedwiththepositiveedgeofanexternallysuppliedclock.
OperatingthefourmemorybanksinaninterleavefashionallowsrandomaccessoperationtooccurahigherratethanispossiblewithstandardDRAMs.Asequentialandgaplessdatarateis
possibledependingonburstlength,CASlatencyandspeedgradeofthedevice.
AutoRefresh(CBR)andSelfRefreshoperationaresupported.Thesedevicesoperatewithasingle
3.3V+/-0.3Vpowersupply.All256MbitcomponentsareavailableinTSOPII-54andTFBGA-54
packages.
INFINEONTechnologies22002-04-23
OrderingInformation
PinDescription:
INFINEONTechnologies32002-04-23
Pinouts(TSOP-54)
INFINEONTechnologies42002-04-23
Pinouts(TFBGA-54)
PinConfigurationforx16devices:
PinConfigurationforx8devices:
PinConfigurationforx4devices:
123789ABCDEFGHJ
123789ABCDEFGHJ
123789ABCDEFGHJ
INFINEONTechnologies52002-04-23
Pinoutforx4,x8&x16organised256M-DRAMs
BlockDiagramfor64Mx4SDRAM(13/11/2addressing)
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BlockDiagramfor32Mx8SDRAM(13/10/2addressing)
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BlockDiagramfor16Mx16SDRAM(13/9/2addressing)
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SignalPinDescription
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INFINEONTechnologies102002-04-23
OperationDefinition
AllofSDRAMoperationsaredefinedbystatesofcontrolsignalsCS,RAS,CAS,WE,andDQMat
thepositiveedgeoftheclock.Thefollowinglistshowsthetruthtablefortheoperationcommands.
INFINEONTechnologies112002-04-23
ModeRegisterSetTableBus(Ax)Register(Mx)

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