HYB39S256160DT-7.5 Fast Delivery |IC PHOENIX CO.,LIMITED

HYB39S256160DT-7.5 ,256-MBit Synchronous DRAMData Sheet, Rev. 1.02, Feb. 2004HYB39S256400D[C/T](L)HYB39S256800D[C/T](L)HYB39S256160D[C/T](L) 256 ..
HYB39S256160FE-6 , 256-MBit Synchronous DRAM
HYB39S256160FE-7 , 256-MBit Synchronous DRAM
HYB39S256400FE-7 , 256-MBit Synchronous DRAM
HYB39S256800DT-7 ,SDRAM ComponentsData Sheet, Rev. 1.02, Feb. 2004HYB39S256400D[C/T](L)HYB39S256800D[C/T](L)HYB39S256160D[C/T](L) 256 ..
HYB39S256800DT-7.5 ,256-MBit Synchronous DRAM
ICS9LPRS511EGLF , Low Power Programmable Timing Control Hub™ for P4™ processor
ICS9LPRS511EGLF , Low Power Programmable Timing Control Hub™ for P4™ processor
ICS9UMS9610CKLFT , PC MAIN CLOCK
ICSLV810FILFT , Buffer/Clock Driver
ICT49FCT3805ASO , 3.3V CMOS BUFFER/CLOCK DRIVER
ICTE-18 ,Diode TVS Single Uni-Dir 18V 1.5KW 2-Pin Case 41A-04 Boxapplications0.210 (5.3) • High temperature soldering guaranteed:O0.190 (4.8) 265 C/10 seconds, 0.37 ..

HYB39S256160DT-7.5
256-MBit Synchronous DRAM

HYB39S256[40/80/16]0D[C/T](L)
Revision History:Rev. 1.022004-02
Previous Version:Rev. 1.012004-01
Previous Version:Rev. 1.02002-06
Table of ContentsPageOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.2Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.1Signal Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
2.2Package P–TSOPII–54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
2.3Package P–TFBGA–54 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2.4Block Diagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11FunctionalDescription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1Operation Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.2Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3Mode Register Definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.3.1Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.5Operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5.1Read and Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5.2DQM Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5.3Suspend Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.5.4Power Down . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19ElectricalCharacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23PackageOutlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Overview
1Overview
1.1FeaturesFully Synchronous to Positive Clock Edge0 to 70°C operating temperatureFour Banks controlled by BA0 & BA1Programmable CAS Latency: 2 & 3Programmable Wrap Sequence: Sequential or InterleaveProgrammable Burst Length: 1, 2, 4, 8 and full pageMultiple Burst Read with Single Write OperationAutomatic and Controlled Precharge CommandData Mask for Read / Write control (x4, x8)Data Mask for byte control (x16)Auto Refresh (CBR) and Self RefreshPower Down and Clock Suspend Mode8192 refresh cycles / 64 ms (7,8 µs)Random Column Address every CLK (1-N Rule)Single 3.3 V ± 0.3 V Power SupplyLVTTL Interface versionsPlastic Packages: P–TSOPII–54 400mil width (x4, x8, x16)Chipsize Packages: P–TFBGA–54 (12 mm x 8 mm)
1.2Description
The HYB39S256[40/80/16]0D[C/T](L) are four bank Synchronous DRAM’s organized as 4banksx16MBitx4,banksx8MBit x8 and 4 banksx4Mbitx16 respectively. These synchronous devices achieve high speed data
transfer rates for CAS-latencies by employing a chip architecture that prefetches multiple bits and then
synchronizes the output data to a system clock. The chip is fabricated with INFINEON’s advanced 0.14 µm
256-MBit DRAM process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products, both electrically
and mechanically. All of the control, address, data input and output circuits are synchronized with the positive edge
of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur at a higher
rate than is possible with standard DRAMs. A sequential and gapless data rate is possible depending on burst
length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single 3.3V ± 0.3V
power supply. All 256-Mbit components are available in P–TSOPII–54 and P–TFBGA–54 packages.
Table1Performance
Overview
Table2Ordering Information
Pin ConfigurationPin Configuration
2.1Signal Pin Description
Table3Signal Pin Description
Pin Configuration
2.2Package P–TSOPII–54
Figure1Pinouts P–TSOPII–54
Table3Signal Pin Description
Pin Configuration
2.3Package P–TFBGA–54
Table4Pin Configuration for x16 devices
Table5Pin Configuration for x8 devices
Table6Pin Configuration for x4 devices
Pin Configuration
2.4Block Diagrams
Figure2Block Diagram for 64M x 4 SDRAM (13/11/2 addressing)
Pin Configuration
Figure3Block Diagram for 32M x 8 SDRAM (13/10/2 addressing)
Pin Configuration
Figure4Block Diagram for 16M x 16 SDRAM (13/9/2 addressing)
FunctionalDescriptionFunctionalDescription
3.1Operation Definition
All of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at the positive
edge of the clock. The following list shows the truth table for the operation commands.
Table7Truth Table: Operation CommandV = Valid, x = Don’t Care, L = Low Level, H = High LevelCKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the commands are
provided.This is the state of the banks designated by BA0, BA1 signals.Power Down Mode can not be entered in a burst cycle. When this command asserted in the burst mode cycle device is in
clock suspend mode.

Partno	Mfg	Dc	Qty	Available	Descript
HYB39S256160DT-7.5 \|HYB39S256160DT75	HIY	N/a	17	avai	256-MBit Synchronous DRAM