HYB39S16320TQ-6 ,256k x2 x32 SGRAMapplications, processes and circuits implemented within components or assemblies.The information de ..
HYB39S16320TQ-6 ,256k x2 x32 SGRAMMemories for Graphics Systems16M Synchronous Graphics RAMSGRAMHYB39S16320TQ-6HYB39S16320TQ-7HYB39S1 ..
HYB39S16320TQ-6 ,256k x2 x32 SGRAMCharacteristics” changedAHEdition 1.1999
HYB39S16320TQ-6
256k x2 x32 SGRAM
Memories for Graphics Systems
16M Synchronous Graphics RAM
SGRAM
HYB39S16320TQ-6
HYB39S16320TQ-7
HYB39S16320TQ-8
Version 2.1.00
Edition 1.1999This edition was realized using the software system FrameMaker.
Published by Siemens AG,
Bereich Halbleiter, Marketing-
Kommunikation, Balanstraße 73,
81541 München© Siemens AG 1999.
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dangered.
Synchronous Graphics RAM
SGRAM
HYB39S16320TQ-6
HYB39S16320TQ-7
HYB39S16320TQ-8
User’s Manual
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Overview
1OverviewThe HYB39S16320TQ are dual bank Synchronous Graphics DRAM’s (SGRAM) organized as 2
banks x 256kBit x 32 with built-in graphics features. These synchronous devices achieve high
speed data transfer rates up to 166 MHz by employing a chip architecture that prefetches multiple
bits and then synchronizes the output data to a system clock. The chip is fabricated with an
advanced 64MBit DRAM process technology.
The device is designed to comply with all JEDEC standards set for synchronous graphics DRAM
products, both electrically and mechanically.
RAS, CAS, WE, DSF and CS are pulsed signals which are examined at the positive edge of each
externally applied clock. Internal chip operating modes are defined by combinations of these
signals. A ten bit address bus accepts address data in the conventional RAS / CAS multiplexing
style. Ten row address bits (A0-A9) and a bank select BA are strobed with RAS. Column address
bits plus a bank select are strobed with CAS.
Prior to any access operation, the CAS latency, burst length and burst sequence must be
programmed into the device by address inputs during a mode register set cycle. An Auto Precharge
function may be enabled to provide a self-timed row precharge. This is initiated at the end of the
burst sequence. In addition, it features the write per bit, the block write and the masked block write
functions. By having a programmable Mode register and Special Mode register, the system can
select the best suitable modes to maximize its performance.
Operating the two memory banks in an interleave fashion allows random access operation to occur
at higher rate than is possible with standard DRAMs. A sequential and gapless data rate of up to
166 MHz is possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported.
These devices operate with a single 3.3V +/- 0.3V power supply and are available in 100pin TQFP
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Overview
1.1FeaturesAll signals fully synchronous to the positiv edge of the system clockProgrammable burst lengths: 1, 2, 4, 8 or full pageBurst data transfer in sequential or interleaved orderBurst read with single writeProgrammable CAS latency: 2, 38 column block write and write-per-bit modesIndependent byte operation via DQM 0..3 interfaceAuto precharge and auto refresh modes2k refresh cycles / 32 msLVTTL compatible I/OHidden autoprecharge for read bursts
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Overview
1.2Pin ConfigurationFigure 1
(top view)
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Overview
1.3Pin Definitions and Functions Table 1
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Overview
1.4Signal Pin Description
Table continued on next page
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Overview
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Overview
1.5Functional Block Diagrams
Figure 2
Block diagram
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Overview
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Functional DescriptionFunctional Description
2.1General
The 16Mb SGRAM is a dual bank 1024 x 256 x 32 DRAM with graphics features of Block Write and
Masked Write. It consists of two banks. Each bank is organized as 1024 rows x 256 columns x 32
bits.
Read and Write accesses are burst oriented. Accesses begin with the registration of an Activate
command which is then followed by a Read or Write command. The address bits registered
coincident with the Active command are used to select the bank and the row to be accessed. BA
selects the bank and address bits A9 -A0 select the row. Address bits A7-A0 registered coincident
with the Read or Write command are used to select the starting column location for the burst
access.
Block Writes are not burst oriented and always apply to eight column locations selected by A7-A3.
DQs registered at Block Write command are used to mask the selected columns. DQs registered
coincident with the Load Special Mode Register command are used as Color Data (LC bit =1) or
Persistent Mask (LM = 1). If LC and LM are both 1 in the same Load Special Mode Register
command cycle, the data of the Mask and the Color Register will be unknown.
2.2Initialization
The default power on state of the mode register is supplier specific and may be undefined. The
following power on and initialization sequence guarantees, that the device is preconditioned to each
users specific needs.
The following sequence is recommended:During power on, all VDD and VDDQ pins must be built up simultaneously to the specified
voltage when the input signals are held in the “NOP” state.The power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies.The CLK signal must be started at the same time.After power on, an initial pause of 200 μs is required.The pause is followed by a precharge of both banks using the precharge command.To prevent data contention on the DQ bus during power on, it is required that the DQM and CKE
pins be held high during the initial pause period.Once all banks have been precharged, the Mode Register Set Command must be issued to
initialize the Mode Register.A minimum of eight Auto Refresh cycles (CBR) are also required.
It is also possible to reverse the last two steps of the initialization procedure:
First send at least 8 CBR commands, then the LMR command.
Failure to follow these steps may lead to unpredictable start-up modes.
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Functional Description
2.3 Mode Register Programming
The Mode Register is used to define: a Burst Length, a Burst type, a Read Latency and an operating
mode. The mode register is programmed via the Load Mode Register command and will retain the
stored information until it is programmed again or the device looses power.The mode register must
be loaded when both banks are idle and the controller must wait the specified time before initiating
the subsequent command. Violating either of these requirements may result in unknown operation.
2.3.1 Burst Length
Read and Write operations to the SGRAM are burst oriented, with the burst length being
programmable. The burst length determines the maximum number of column locations that can be
accessed for a given Read or Write command. Burst lengths of 1, 2, 4, or 8 locations are available
for both the sequential and the interleaved burst types and a Full Page Burst is available for the
sequential type. The Full Page Burst is used in conjunction with the Burst Terminate command to
generate arbitrary burst lengths.
When a Read or Write command is issued, a block of columns equal to the burst length is selected.
The block is defined by address bits A7-A1 when the burst length is set to 2, by A7-A2 for burst
length set to 4 and by A7-A3 for burst length set to 8. The lower order bit(s) are used to select the
starting location within the block. The burst will wrap within the block if a boundary is reached.
2.3.2Burst Type
Accesses within a given burst may be programmed to be either sequential or interleaved and the
type is selected based on the setting of BT bit in the mode register. If BT is set to “0”, the burst type
is sequential, if BT is “1”, the burst type is interleave.
2.3.3 Read Latency
The Read Latency is the delay in clock cycles between the registration of a Read command and the
availability of the first piece of output data. The latency can be set to 2 or 3 clocks. If a Read
command is registered at clock edge n and the Read Latency is 2 clocks, the data will be available
by clock edge n+2. The DQs will start driving already one cycle earlier (n+1).
2.3.4Color Register
The Siemens 16M SGRAM offers two Color Registers. If Bit M7 is set to “1”, two Color Register
mode is specified.
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Functional Description
2.3.5Operation Mode
In normal operation, the bits M8 and M9 of Mode Register (MR) are set “0”. The programmed burst
length applies to both read and write bursts. When bit M8 is set to “1”, burst read and single write
mode is selected.
Test modes and reserved states should not be used because unknown operation or incompatibility
with future versions may result.
2.4Load Special Mode Register (LSMR)
The Special Mode Register command is used to load the mask and color registers, which are used
in Block Write and Masked Write cycles.The data to be written to either the color registers or the
Mask Register is applied to the DQs and the control information is applied to the address inputs.
During a LSMR cycle, if the address bit A6 is “1”, and all other address inputs are “0”, the Color
Register 0 will be loaded with the data on the DQs. If the address bits A6 and A7 are both set equal
to “1” and Mode Register M7 bit was already set to “1”, Color Register 1 will be loaded with the data
on the DQs.This color data is used for Block Write cycles. Similarly, when input A5 is “1”, and all
other address inputs are “0” during a LSMR cycle, the mask register will be loaded with the data on
the DQs. Never Set bit A5 to “1” when A6 and/or A7 are set equal to “1” in the same Load Special
Mode Register cycle to avoid unknown operation.
2.4.1Color Registers
Two Color Registers (Color Register 0 and Color Register 1) are available in the devices. Each color
register is a 32-bit register which supplies the data during Block Write cycles. The Color Register is
loaded via a Load Special Mode Register command, as shown in the Function Truth table and will
retain data until loaded again with a new data or until power is removed from the SGRAM.
2.4.2Mask Register
The Mask Register (or the Write-per-Bit mask register) is a 32-bit register which acts as a per-bit
mask during Masked Write and Masked Block Write cycles. The Mask Register is loaded via the
Load Special Mode Register command and will retain data until loaded again or until power is
removed from the SGRAM.
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Functional Description
2.5Commands
The Function Truth Table provides a quick reference of available commands.
Table 2
Function Truth Table
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Functional Description
Note 01 All inputs are latched on the rising edge of the CLK.
Note 02 LMR, REF and SREF commands should be issued only after both banks are deactivated (PREAL
command).
Note 03. ACT and ACTM command should be issued only after the corresponding bank has been deactivated
(PRE command).
Note 04. WR, WRA, RD, RDA should be issued after the corresponding bank has been activated (ACT command).
Note 05. Auto Precharge command is not valid for full-page burst.
Note 06. BW and BWA commands use mask register data only after ACTM command. DQM byte masking is
active regardless of WPB mask.
Note 07. Loading Mask Register: Initiate an LSMR cycle with address pin A5 =1 to load the Mask register with the
Mask data present on DQ pins. Except A5 , all other address pins must be “0” during LSMR cycle while
loading the Mask Register
Note 08. Loading Color Register: Initiate an LSMR cycle with address pin A6 =1 to load the Color register with the
Color input data on DQ pins. Address pin A7 selects Color register. Except A6 and A7 , all other address
pins must be “0” during LSMR cycle while loading a Color register. If one Color register mode is enabled,
all address pins, except A6, must be “0” during LSMR cycle.
Note 09. If BW or BWA operation is initiated and 2-Color Register Mode is initialized by the Mode Register,
address A0 selects the desired Color Register for the operation. If A0 = 0, Color Register 0 will be used,
if A0 = 1, Color Register 1.
Note 010. Any Write or Block Write cycles to the selected bank/row while active will be masked according to the
contents of the mask register, in addition to the DQM signals and the column/byte mask information (the
later for Block Writes only).
Note 011. Block Writes are not burst oriented and always apply to the eight column locations selected by A7-A3 .
Note 012. Addressline A9 is always “X” with the exception of two commands:
In LMR and LSMR commands it provides Opcode (see description Mode and Special Mode Register)
In ACT and ACTM commands it provides the addressbit 9 of the Row Address.
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Functional Description
2.5.1Address Input for Mode Set (Mode Register Functions)
Figure 3Address Bus (Ax)Mode Register (Mx)
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Functional Description
2.5.2Burst Length and Sequence:
Table 3
Table 4
Table 5
Burst of two
Burst of four
Burst of eight
Full Page Burst
Full page Burst is an extension of the above tables of sequential
addressing with the burst length being 256.
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Functional Description
2.5.3Special Mode Register Functions:
Table 6
Note:If only one Color Register is in use, A7 is Don’t Care.
Table 7
2.5.4Device Deselect (INHBT)
The device deselect or inhibit function prevents commands from being executed by the SGRAM,
regardless of whether the CLK signal is enabled. The device is effectively deactivated (CS is high).
2.5.5No Operation (NOP)
The NOP command is used to perform a no operation to an SGRAM which is selected (CS is low).
This prevents unwanted commands being registered during idle or wait states. The execution of the
command(s) already in progress will not be affected
2.5.6Load Mode Register (LMR)
The Mode Register is loaded via address input pins A9 - A0 . The LMR command can only be issued
when both banks are idle, and a subsequent executable command can not be issued until 2 CLK
cycle Latency is met.
Special Mode Register naming conventions
