HYB39S128400CT-8 ,128-MBit Synchronous DRAMapplications Programmable Burst Length: -7.5 for PC 133 3-3-3
HYB39S128800CT-7 ,128Mbit Synchronous DRAMsapplications1, 2, 4, 8 and full page-8 for PC100 2-2-2
HYB39S128800CT-7.5 ,SDRAM Componentsapplications1, 2, 4, 8 and full page-8 for PC100 2-2-2
HYB39S128800FE-7 , 128-MBit Synchronous DRAM
HYB39S16160AT-10 , 16 MBit Synchronous DRAM
HYB39S16160AT-8 , 16 MBit Synchronous DRAM
ICS9LPRS511EGLF , Low Power Programmable Timing Control Hub™ for P4™ processor
ICS9LPRS511EGLF , Low Power Programmable Timing Control Hub™ for P4™ processor
ICS9UMS9610CKLFT , PC MAIN CLOCK
ICSLV810FILFT , Buffer/Clock Driver
ICT49FCT3805ASO , 3.3V CMOS BUFFER/CLOCK DRIVER
ICTE-18 ,Diode TVS Single Uni-Dir 18V 1.5KW 2-Pin Case 41A-04 Boxapplications0.210 (5.3) • High temperature soldering guaranteed:O0.190 (4.8) 265 C/10 seconds, 0.37 ..
HYB39S128160CT-8-HYB39S128160CTL-7.5-HYB39S128400CT-8
128-MBit Synchronous DRAM
HYB39S128400/800/160CT(L)
128-MBit Synchronous DRAMINFINEON Technologies19.01
The HYB39S128400/800/160CT are four bank Synchronous DRAM’s organized as 4
banks×8MBit x4, 4 banks×4MBit x8 and 4 banks×2Mbit x16 respectively. These synchronous
devices achieve high speed data transfer rates by employing a chip architecture that prefetches
multiple bits and then synchronizes the output data to a system clock. The chip is fabricated using
the Infineon advanced 0.17 micron process technology.
The device is designed to comply with all industry standards set for synchronous DRAM products,
both electrically and mechanically. All of the control, address, data input and output circuits are
synchronized with the positive edge of an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at a higher rate than is possible with standard DRAMs. A sequential and gapless data rate is
possible depending on burst length, CAS latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. These devices operate with a single
3.3V±0.3V power supply and are available in TSOPII packages.
High Performance:Single Pulsed RAS InterfaceFully Synchronous to Positive Clock Edge0 to 70°C operating temperatureFour Banks controlled by BA0 & BA1Programmable CAS Latency: 2, 3Programmable Wrap Sequence: Sequential
or InterleaveProgrammable Burst Length:
1, 2, 4, 8 and full pageMultiple Burst Read with Single Write
OperationAutomatic and Controlled Precharge
CommandData Mask for Read/Write Control (x4, x8)Data Mask for byte control (x16)Auto Refresh (CBR) and Self RefreshPower Down and Clock Suspend Mode4096 Refresh Cycles / 64 msRandom Column Address every CLK
(1-N Rule)Single 3.3V±0.3V Power SupplyLVTTL InterfacePlastic Packages:
P-TSOPII-54 400mil x 875 mil width
(x4, x8, x16)-7for PC 133 2-2-2 applications
-7.5for PC 133 3-3-3 applicationsfor PC100 2-2-2 applications
128-MBit Synchronous DRAM
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Ordering Information
Pin Definitions and Functions
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Pin Configuration for x4, x8 & x16 Organized 128M-DRAMs
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Functional Block Diagrams
Block Diagram: 32M x4 SDRAM (12 / 11 / 2 addressing)
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Block Diagram: 16M x8 SDRAM (12 / 10 / 2 addressing)
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Block Diagram: 8M x16 SDRAM (12 / 9 / 2 addressing)
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Signal Pin Description
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Signal Pin Description (cont’d)
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Operation DefinitionAll of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and DQM at
the positive edge of the clock. The following list shows the truth table for the operation commands.
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Address Inputs for Mode Register Set Operation
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Power On and InitializationThe default power on state of the mode register is supplier specific and may be undefined. The
following power on and initialization sequence guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and
initialized in a predefined manner. During power on, all VDD and VDDQ pins must be built up
simultaneously to the specified voltage when the input signals are held in the “NOP” state. The
power on voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. The CLK
signal must be started at the same time. After power on, an initial pause of 200μs is required
followed by a precharge of all banks using the precharge command. To prevent data contention on
the DQ bus during power on, it is required that the DQM and CKE pins be held high during the initial
pause period. Once all banks have been precharged, the Mode Register Set Command must be
issued to initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also
required.These may be done before or after programming the Mode Register. Failure to follow these
steps may lead to unpredictable start-up modes.
Programming the Mode RegisterThe Mode register designates the operation mode at the read or write cycle. This register is divided
into 4 fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit to
program the column access sequence in a burst cycle (interleaved or sequential), a CAS Latency
Field to set the access time at clock cycle and a Operation mode field to differentiate between
normal operation (Burst read and burst Write) and a special Burst Read and Single Write mode.
After the initial power up, the mode set operation must be done before any activate command. Any
content of the mode register can be altered by re-executing the mode set command. All banks must
be in precharged state and CKE must be high at least one clock before the mode set operation. After
the mode register is set, a Standby or NOP command is required. Low signals of RAS, CAS, and
WE at the positive edge of the clock activate the mode set operation. Address input data at this
timing defines parameters to be set as shown in the previous table.
Read and Write OperationWhen RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle
starts. According to address data, a word line of the selected bank is activated and all of sense
amplifiers associated to the wordline are set. A CAS cycle is triggered by setting RAS high and CAS
low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define either
a read (WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 143MHz data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page. Column
addresses are segmented by the burst length and serial data accesses are done within this
boundary. The first column address to be accessed is supplied at the CAS timing and the
subsequent addresses are generated automatically by the programmed burst length and its
sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’,
then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5.
Full page burst operation is only possible using sequential burst type and page length is a function
of the I/O organisation and column addressing. Full page burst operation does not self terminate
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once the burst length has been reached. In other words, unlike burst length of 2, 4, and 8, full page
burst continues until it is terminated using another command.
Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column
address are possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the
refresh interval time limits the number of random column accesses. A new burst access can be
done even before the previous burst ends. The interrupt operation at every clock cycle is supported.
When the previous burst is interrupted, the remaining addresses are overridden by the new address
with the full burst length. An interrupt which accompanies an operation change from a read to a write
is possible by exploiting DQM to avoid bus contention.
When two or more banks are activated sequentially, interleaved bank read or write operations are
possible. With the programmed burst length, alternate access and precharge operations on two or
more banks can realize fast serial data access modes among many different pages. Once two or
more banks are activated, column to column interleave operation can be performed between
different pages.
Refresh ModeSDRAM has two refresh modes, Auto Refresh and Self Refresh. Auto Refresh is similar to the CAS
-before-RAS refresh of conventional DRAMs. All of banks must be precharged before applying any
refresh mode. An on-chip address counter increments the word and the bank addresses and no
bank information is required for both refresh modes.
The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are
held high at a clock timing. The mode restores word line after the refresh and no external precharge
Burst Length and Sequence
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command is necessary. A minimum tRC time is required between two automatic refreshes in a burst
refresh mode. The same rule applies to any access command after the automatic refresh operation.
The chip has an on-chip timer and the Self Refresh mode is available. It enters the mode when RAS,
CAS, and CKE are low and WE is high at a clock timing. All of external control signals including the
clock are disabled. Returning CKE to high enables the clock and initiates the refresh exit operation.
After the exit command, at least one tRC delay is required prior to any access command.
DQM FunctionDQM has two functions for data I/O read and write operations. During reads, when it turns to “high”
at a clock timing, data outputs are disabled and become high impedance after two clock delay (DQM
Data Disable Latency tDQZ). It also provides a data mask function for writes. When DQM is activated,
the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero clocks).
Suspend ModeDuring normal access mode, CKE is held high enabling the clock. When CKE is low, it freezes the
internal clock and extends data read and write operations. One clock delay is required for mode
entry and exit (Clock Suspend Latency tCSL).
Power DownIn order to reduce standby power consumption, a power down mode is available. All banks must be
precharged and the necessary Precharge delay (tRP) must occur before the SDRAM can enter the
Power Down mode. Once the Power Down mode is initiated by holding CKE low, all of the receiver
circuits except CLK and CKE are gated off. The Power Down mode does not perform any refresh
operations, therefore the device can’t remain in Power Down mode longer than the Refresh period
(tREF) of the device. Exit from this mode is performed by taking CKE “high”. One clock delay is
required for power down mode entry and exit.
Auto PrechargeTwo methods are available to precharge SDRAMs. In an automatic precharge mode, the CAS
timing accepts one extra address, CA10, to determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function
is initiated. If CA10 is high when a Write Command is issued, the Write with Auto-Precharge function
is initiated. The SDRAM automatically enters the precharge operation a time delay equal to tWR
(Write recovery time) after the last data in.
Precharge CommandThere is also a separate precharge command available. When RAS and WE are low and CAS is
high at a clock timing, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are
used to define banks as shown in the following list. The precharge command can be imposed one
clock before the last data out for CAS latency = 2, two clocks before the last data out for CAS
latency= 3 and three clocks before the last data out for CAS latency= 4. Writes require a time delay
tWR from the last data out to apply the precharge command.
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Burst TerminationOnce a burst read or write operation has been initiated, there are several methods in which to
terminate the burst operation prematurely. These methods include using another Read or Write
Command to interrupt an existing burst operation, use a Precharge Command to interrupt a burst
cycle and close the active bank, or using the Burst Stop Command to terminate the existing burst
operation but leave the bank open for future Read or Write Commands to the same page of the
active bank. When interrupting a burst with another Read or Write Command care must be taken to
avoid DQ contention. The Burst Stop Command, however, has the fewest restrictions making it the
easiest method to use when terminating a burst operation before it has been completed. If a Burst
Stop command is issued during a burst write operation, then any residual data from the burst write
cycle will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is
registered will be written to the memory.
Bank Selection by Address Bits
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Electrical Characteristics
Absolute Maximum RatingsOperating Temperature Range.......................................................................................0 to + 70 °C
Storage Temperature Range.................................................................................. – 55 to + 150 °C
Input/Output Voltage......................................................................................... – 0.3 to VDD + 0.3 V
Power Supply Voltage VDD/VDDQ.............................................................................. – 0.3 to + 4.6 V
Power Dissipation.......................................................................................................................1 W
Data out Current (short circuit)...............................................................................................50 mA
Note:Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
Recommended Operation and DC Characteristics TA = 0 to 70 °C; VSS = 0 V; VDD,VDDQ = 3.3 V ± 0.3 V
Notes
1.)All voltages are referenced to VSS.
2.)VIH may overshoot to VDD + 2.0 V for pulse width of < 4 ns with 3.3 V. VIL may undershoot to–2.0V for pulse
width < 4.0 ns with 3.3 V. Pulse width measured at 50% points with amplitude measured peak to DC reference.
CapacitanceTA = 0 to 70 °C; VDD = 3.3 V ± 0.3 V, f = 1 MHz
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NotesThese parameters depend on the cycle rate. These values are measured at 133MHz for -7 &
-7.5 and at 100MHz for -8 parts. Input signals are changed once during tCK.These parameters are measured with continuous data stream during read access and all DQ
toggling. CL=3 and BL=4 is assumed and the VDDQ current is excluded.
Operating CurrentsTA = 0 to 70°C, VDD = 3.3V ± 0.3V
(Recommended Operating Conditions unless otherwise noted)
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AC Characteristics 1, 2
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns
Clock and Clock Enable
Setup and Hold Times
Common Parameters
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NotesFor proper power-up see the operation section of this data sheet.AC timing tests have VIL=0.4V and VIH=2.4V with the timing referenced to the 1.4V crossover
point. The transition time is measured between VIH and VIL. All AC measurements assume=1ns with the AC output load circuit shown in figure below. Specified tAC and tOH parameters
are measured with a 50pF only, without any resistive termination and with a input signal of 1V /
ns edge rate between 0.8V and 2.0V.
Refresh Cycle
Read Cycle
Write Cycle
AC Characteristics (cont’d)1, 2
TA = 0 to 70 °C; VSS = 0 V; VDD = 3.3 V ± 0.3 V, tT = 1 ns
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Package Outlines
Timing Diagrams1. Bank Activate Command Cycle page 22
2. Burst Read Operationpage 23
3. Read Interrupted by a Readpage 24
4. Read to Write Interval page 24
4.1 Read to Write Interval page 24
4.2 Minimum Read to Write Interval page 25
4.3 Non-Minimum Read to Write Intervalpage 25
5. Burst Write Operation page 26
6. Write and Read Interrupt page 27
6.1 Write Interrupted by a Write page 27
6.2 Write Interrupted by Read page 27
7. Burst Write & Read with Auto-Precharge page 28
7.1 Burst Write with Auto-Precharge page 28
7.2 Burst Read with Auto-Prechargepage 28
8. AC- Parameterspage 29
8.1 AC Parameters for a Write Timingpage 29
8.2 AC Parameters for a Read Timingpage 30
9. Mode Register Setpage 31
10. Power on Sequence and Auto Refresh (CBR)page 32
11. Clock Suspension (using CKE)page 33
11. 1 Clock Suspension During Burst Read CAS Latency = 2page 33
11. 2 Clock Suspension During Burst Read CAS Latency = 3page 34
11. 3 Clock Suspension During Burst Write CAS Latency = 2page 35
11. 4 Clock Suspension During Burst Write CAS Latency = 3page 36
12. Power Down Mode and Clock Suspendpage 37
13. Self Refresh ( Entry and Exit )page 38
14. Auto Refresh ( CBR )page 39
15. Random Column Read ( Page within same Bankpage 40
15.1 CAS Latency = 2page 40
15.2 CAS Latency = 3page 41
16. Random Column Write ( Page within same Bank)page 42
16.1 CAS Latency = 2page 42
16.2 CAS Latency = 3page 43
17. Random Row Read ( Interleaving Banks) with Prechargepage 44
17.1 CAS Latency = 2page 44
17.2 CAS Latency = 3page 45
18. Random Row Write ( Interleaving Banks) with Prechargepage 46
18.1 CAS Latency = 2page 46
18.2 CAS Latency = 3page 47
19. Precharge Termination of a Burst page 48
20. Full Page Burst Operationpage 49
20.1 Full Page Burst Read, CAS Latency = 2page 49
18.2 Full Page Burst Write, CAS Latency = 3page 50
1. Bank Activate Command Cycle
2. Burst Read Operation
3. Read Interrupted by a Read
4. Read to Write Interval
4.1 Read to Write Interval
4 2. Minimum Read to Write Interval
4. 3. Non-Minimum Read to Write Interval
5. Burst Write Operation
6. Write and Read Interrupt6.1 Write Interrupted by a Write
6.2 Write Interrupted by a Read
