HYB39L256160AC-7.5 ,Specialty DRAMsHYB39L256160AC/T256MBit 3.3V Mobile-RAM256 MBit Synchronous Low-Power DRAMData Sheet Revision Dec. ..
HYB39L256160AC-8 ,256 MBit Synchronous Low-Power DRAMHYB39L256160AC/T256MBit 3.3V Mobile-RAM256 MBit Synchronous Low-Power DRAMData Sheet Revision Dec. ..
HYB39L256160AT-7.5 ,Specialty DRAMsHYB39L256160AC/T256MBit 3.3V Mobile-RAM256 MBit Synchronous Low-Power DRAMData Sheet Revision Dec. ..
HYB39S128160CT-7 ,128Mbit Synchronous DRAMsapplications Programmable Burst Length: -7.5 for PC 133 3-3-3
HYB39S128160CT-7 ,128Mbit Synchronous DRAMsHYB 39S128400/800/160CT(L)128-MBit Synchronous DRAM128-MBit Synchronous DRAM High Performance: M ..
HYB39S128160CT-7.5 ,SDRAM ComponentsHYB 39S128400/800/160CT(L)128-MBit Synchronous DRAM128-MBit Synchronous DRAM High Performance: M ..
ICS9LPRS511EGLF , Low Power Programmable Timing Control Hub™ for P4™ processor
ICS9LPRS511EGLF , Low Power Programmable Timing Control Hub™ for P4™ processor
ICS9UMS9610CKLFT , PC MAIN CLOCK
ICSLV810FILFT , Buffer/Clock Driver
ICT49FCT3805ASO , 3.3V CMOS BUFFER/CLOCK DRIVER
ICTE-18 ,Diode TVS Single Uni-Dir 18V 1.5KW 2-Pin Case 41A-04 Boxapplications0.210 (5.3) • High temperature soldering guaranteed:O0.190 (4.8) 265 C/10 seconds, 0.37 ..
HYB39L256160AC-7.5-HYB39L256160AT-7.5
Specialty DRAMs
HYB39L256160AC/T
256MBit3.3VMobile-RAMINFINEON Technologies AG12002-12-20
DescriptionThe HYB39L256160AC Mobile-RAM is a new generation of low power, four bank Synchronous
DRAM’s organized as 4banksx4Mbitx16. These synchronous Mobile-RAMs achieve high speed
data transfer rates by employing a chip architecture that prefetches multiple bits and then
synchronizes the output data to a system clock.
All of the control, address, data input and output circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher rate. A sequential and gapless data rate is possible depending on burst length, CAS
latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. The device operates with a single
3.3V �0.3V power supply.
Compared to conventional SDRAM the self-refresh current is further reduced. The Mobile-RAM
devices are available in FBGA “chip-size” or TSOPII packages.
Features16Mbit x16 organisationVDD = VDDQ = 3.3VFully Synchronous to Positive Clock EdgeFour Banks controlled by BA0 & BA1Programmable CAS Latency: 2, 3Programmable Wrap Sequence: Sequential
or InterleaveAutomatic and Controlled Precharge
CommandProgrammable Burst Length: 1, 2, 4, 8 and
full pageData Mask for byte controlAuto Refresh (CBR) 8192 Refresh Cycles / 64msVery low Self Refresh currentPower Down and Clock Suspend ModeRandom Column Address every CLK
(1-N Rule)P-TFBGA-54, with 9 x 6 ball array with depopulated rows, 12 x 8 mm2P-TSOPII-54 alternate packageOperating Temperature Range
Commerical (00 to 700C)
256MBit Synchronous Low-Power DRAM
Data Sheet Revision Dec. 2002
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256MBit3.3VMobile-RAMINFINEON Technologies AG22002-12-20
Ordering Information
Pin Definitions and Functions
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Pin Configuration for BGA devices< Top-view >
123789ABCDEFGHJ
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Pin Configuration for TSOP devices
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Functional Block Diagrams
Block Diagram: 16Mb x16 SDRAM (13 / 9 / 2 addressing)
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Signal Pin Description
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Operation DefinitionAll of SDRAM operations are defined by states of control signals CS, RAS, CAS, WE, and xDQM at
the positive edge of the clock. The following list shows the truth table for the operation commands.
NotesV = Valid, x = Don’t Care, L = Low Level, H = High Level.CKEn signal is input level when commands are provided, CKEn-1 signal is input level one clock before the
commands are provided.This is the state of the banks designated by BA0, BA1 signals.Address Input for Mode Set (Mode Register Operation)Power Down Mode can not be entered during a burst cycle. When this command is asserted during a burst
cycle the device enters Clock Suspend Mode.
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Mode Register TableHYB39L256160AC/T
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Power-On and InitializationThe default power-on state of the mode register is supplier specific and may be undefined. The
following power on and initialization sequence guarantees the device is preconditioned to each
users specific needs. Like a conventional DRAM, the Synchronous DRAM must be powered up and
initialized in a predefined manner. VDD must be applied before or at the same time as VDDQ to the
specified voltage when the input signals are held in the “NOP” or “DESELECT” state. The power on
voltage must not exceed VDD+0.3V on any of the input pins or VDD supplies. The CLK signal must
be started at the same time. After power on, an initial pause of 200�s is required followed by a
precharge of all banks using the precharge command. To prevent data contention on the DQ bus
during power on, it is required that the DQM and CKE pins be held high during the initial pause
period. Once all banks have been precharged, the Mode Register Set Command must be issued to
initialize the Mode Register. A minimum of eight Auto Refresh cycles (CBR) are also required.These
may be done before or after programming the Mode Register. Failure to follow these steps may lead
to unpredictable start-up modes.
Programming the Mode RegisterThe Mode Register designates the operation mode at the read or write cycle. This register is divided
into 4 fields. A Burst Length Field to set the length of the burst, an Addressing Selection bit to
program the column access sequence in a burst cycle (interleaved or sequential), and a CAS
Latency Field to set the access time at clock cycle, an The mode set operation must be done before
any activate command after the initial power up. Any content of the mode register can be altered by
re-executing the mode set command. All banks must be in precharged state and CKE must be high
at least one clock before the mode set operation. After the mode register is set, a Standby or NOP
command is required. Low signals of RAS, CAS, and WE at the positive edge of the clock activate
the mode set operation. Address input data at this timing defines parameters to be set as shown in
the previous table. BA0 and BA1 have to be set to “0” to enter the Mode Register.
Read and Write OperationWhen RAS is low and both CAS and WE are high at the positive edge of the clock, a RAS cycle
starts. According to address data, a word line of the selected bank is activated and all of sense
amplifiers associated to the wordline are set. A CAS cycle is triggered by setting RAS high and CAS
low at a clock timing after a necessary delay, tRCD, from the RAS timing. WE is used to define either
a read (WE = H) or a write (WE = L) at this stage.
SDRAM provides a wide variety of fast access modes. In a single CAS cycle, serial data read or
write operations are allowed at up to a 133MHz data rate. The numbers of serial data bits are the
burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8 and full page. Column
addresses are segmented by the burst length and serial data accesses are done within this
boundary. The first column address to be accessed is supplied at the CAS timing and the
subsequent addresses are generated automatically by the programmed burst length and its
sequence. For example, in a burst length of 8 with interleave sequence, if the first address is ‘2’,
then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5.
Full page burst operation is only possible using the sequential burst type and page length is a
function of the I/O organisation and column addressing. Full page burst operation do not self
terminate once the burst length has been reached. In other words, unlike burst length of 2, 4 and 8,
full page burst continues until it is terminated using another command.
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Similar to the page mode of conventional DRAM’s, burst read or write accesses on any column
address are possible once the RAS cycle latches the sense amplifiers. The maximum tRAS or the
refresh interval time limits the number of random column accesses. A new burst access can be
done even before the previous burst ends. The interrupt operation at every clock cycle is supported.
When the previous burst is interrupted, the remaining addresses are overridden by the new address
with the full burst length. An interrupt which accompanies an operation change from a read to a write
is possible by exploiting DQM to avoid bus contention.
When two or more banks are activated sequentially, interleaved bank read or write operations are
possible. With the programmed burst length, alternate access and precharge operations on two or
more banks can realize fast serial data access modes among many different pages. Once two or
more banks are activated, column to column interleave operation can be performed between
different pages. When the partial array activation is set, data will get lost when self-refresh is used
in all non activated banks.
Refresh ModeMobile-RAM has two refresh modes, Auto Refresh and Self Refresh.
Auto-RefreshAuto Refresh is similar to the CAS-before-RAS refresh of earlier DRAMs. All banks must be
precharged before applying any refresh mode. An on-chip address counter increments the word
and the bank addresses. No bank information is required for both refresh modes.
The chip enters the Auto Refresh mode, when RAS and CAS are held low and CKE and WE are
held high at a clock edge. The mode restores word line after the refresh and no external precharge
Burst Length and Sequence
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command is necessary. A minimum tRC time is required between two automatic refreshes in a burst
refresh mode. The same rule applies to any access command after the automatic refresh operation.
In Auto-Refresh mode all banks are refreshed, independed if the partial activation has been set.
Self-RefreshThe chip has an on-chip timer that is used when the Self Refresh mode is entered. The self-refresh
command is asserted with RAS, CAS, and CKE low and WE high at a clock edge. All external
control signals including the clock are disabled. Returning CKE to high enables the clock and
initiates the refresh exit operation. After the exit command, at least one tRC delay is required prior to
any command. After self refresh exit an autorefresh command is recommended due to the chance
of an exit just before the next internal refresh is executed.
DQM FunctionDQMx has two functions for data I/O read and write operations. During reads, when it turns to “high”
at a clock edge, data outputs are disabled and become high impedance after two clock periods
(DQM Data Disable Latency tDQZ). It also provides a data mask function for writes. When DQM is
activated, the write operation at the next clock is prohibited (DQM Write Mask Latency tDQW = zero
clocks).
Suspend ModeDuring normal access, CKE is held high enabling the clock. When CKE is low, it freezes the internal
clock and extends data read and write operations. One clock delay is required for mode entry and
exit (Clock Suspend Latency tCSL).
Power DownIn order to reduce standby power consumption, a power down mode is available. All banks must be
precharged before the Mobile-RAM can enter the Power Down mode. Once the Power Down mode
is initiated by holding CKE low, all receiver circuits except for CLK and CKE are gated off. The
Power Down mode does not perform any refresh operations, therefore the device can’t remain in
Power Down mode longer than the Refresh period (tREF) of the device. Exit from this mode is
performed by taking CKE “high”. One clock delay is required for power down mode entry and exit.
Auto PrechargeTwo methods are available to precharge Mobile-RAMs. In an automatic precharge mode, the CAS
timing accepts one extra address, CA10, to determine whether the chip restores or not after the
operation. If CA10 is high when a Read Command is issued, the Read with Auto-Precharge function
is initiated. If CA10 is high when a Write Command is issued, the Write with Auto-Precharge function
is initiated. The Mobile-RAM automatically enters the precharge operation after tWR (Write recovery
time) following the last data in.
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Precharge CommandThere is also a separate precharge command available. When RAS and WE are low and CAS is
high at a clock edge, it triggers the precharge operation. Three address bits, BA0, BA1 and A10 are
used to define banks as shown in the following list. The precharge command can be imposed one
clock before the last data out for CAS latency = 2 and two clocks before the last data out for CAS
latency= 3. Writes require a time delay tWR from the last data out to apply the precharge command.
Bank Selection by Address Bits
Burst TerminationOnce a burst read or write operation has been initiated, there are several methods used to terminate
the burst operation prematurely. These methods include using another Read or Write Command to
interrupt an existing burst operation, using a Precharge Command to interrupt a burst cycle and
close the active bank, or using the Burst Stop Command to terminate the existing burst operation
but leave the bank open for future Read or Write Commands to the same page of the active bank.
When interrupting a burst with another Read or Write Command care must be taken to avoid DQ
contention. The Burst Stop Command, however, has the fewest restrictions making it the easiest
method to use when terminating a burst operation before it has been completed. If a Burst Stop
command is issued during a burst write operation, then any residual data from the burst write cycle
will be ignored. Data that is presented on the DQ pins before the Burst Stop Command is registered
will be written to the memory.
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Electrical Characteristics
Absolute Maximum RatingsOperating Case Temperature Range (commercial) ....................................................... 0 to +70�C
Storage Temperature Range ................................................................................... –55 to +150�C
Input/Output Voltage VIN, VOUT ......................................................................... –1.0 to VDD + 0.5V
Input/Output Voltage VIN, VOUT ................................................................................. –1.0 to +4.6V
Power Supply Voltages VDD, VDDQ ............................................................................ –1.0 to +4.6V
Power Dissipation ................................................................................................................... 0.7W
Data out Current (short circuit) .............................................................................................. 50mA
Note:Stresses above those listed under “Absolute Maximum Ratings” may cause permanent
damage of the device. Exposure to absolute maximum rating conditions for extended
periods may affect device reliability.
NotesAll voltages are referenced to VSS.2.VIH may overshoot to VDDQ+2.0V for pulse width of <4ns with VDDQ=3.3V.
VIL may undershoot to–2.0V for pulse width <4.0ns with VDDQ=3.3V.
Pulse width measured at 50% points with amplitude measured peak to DC reference.
Recommended Operation and DC Characteristics TCASE = 0 to 70�C (commercial),
VSS = 0V
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Capacitance
NotesThese parameters depend on the frequency. These values are measured at 133MHz for -7.5 and at 100MHzfor -8 parts. Input signals are changed once during tCK. If the devices are operating at a frequency less than the
maximum operation frequency, these current values are reduced.These parameters are measured with continuous data stream during read access and all DQ toggling. CL=3and BL=4 is used and the VDDQ current is excluded.
TCASE = 0 to 70 �C (commercial),
f = 1 MHz
Operating CurrentsTCASE = 0 to 70�C (commercial)
(Recommended Operating Conditions unless otherwise noted)
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AC Characteristics 1, 2
TCASE = 0 to 70 �C (commercial),
(Recommended Operating Conditions unless otherwise noted)
Clock and Clock Enable
Setup and Hold Times
Common Parameters
Refresh Cycle
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Read Cycle
Write Cycle
AC Characteristics (cont’d)1, 2
TCASE = 0 to 70 �C (commercial),
(Recommended Operating Conditions unless otherwise noted)
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256MBit3.3VMobile-RAMINFINEON Technologies AG182002-12-20
NotesFor proper power-up see the operation section of this data sheet.AC timing tests are referenced to the 0.9V crossover point. The transition time is measured
between VIH and VIL. All AC measurements assume tT=1ns with the AC output load circuit
(details will be defined later). Specified tAC and tOH parameters are measured with a 30pF only,
without any resistive termination and with a input signal of 1V/ns edge rate.If clock rising time is longer than 1 ns, a time (tT/2-0.5) ns has to be added to this parameter.If tT is longer than 1ns, a time (tT-1) ns has to be added to this parameter.These parameter account for the number of clock cycle and depend on the operating frequency
of the clock, as follows:
the number of clock cycle = specified value of timing period (counted in fractions as a whole
number)Access time from clock tAC is 4.6ns for -7.5 components with no termination and 0pF load,
Data out hold time tOH is 1.8ns for -7.5 components with no termination and 0pF load.The write recovery time of tWR = 14ns cycles allows the use of one clock cycle for the write
recovery time when the memory operation frequency is equal or less than 72MHz. For all
memory operation frequencies higher than 72MHz two clock cycles for tWR are mandatory.
INFINEON recommends to use two clock cylces for the write recovery time in all applications.
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Timing Diagrams1. Bank Activate Command Cycle
2. Burst Read Operation
3. Read Interrupted by a Read
4. Read to Write Interval
4.1 Read to Write Interval
4.2 Minimum Read to Write Interval
4.3 Non-Minimum Read to Write Interval
5. Burst Write Operation
6. Write and Read Interrupt
6.1 Write Interrupted by a Write
6.2 Write Interrupted by Read
7. Burst Write & Read with Auto-Precharge
7.1 Burst Write with Auto-Precharge
7.2 Burst Read with Auto-Precharge
8. AC- Parameters
8.1 AC Parameters for a Write Timing
8.2 AC Parameters for a Read Timing
9. Mode Register Set
10. Power on Sequence and Auto Refresh (CBR)
11. Clock Suspension (using CKE)
11. 1 Clock Suspension During Burst Read CAS Latency = 2
11. 2 Clock Suspension During Burst Read CAS Latency = 3
11. 3 Clock Suspension During Burst Write CAS Latency = 2
11. 4 Clock Suspension During Burst Write CAS Latency = 3
12. Power Down Mode and Clock Suspend
13. Self Refresh ( Entry and Exit )
14. Auto Refresh ( CBR )
15. Random Column Read ( Page within same Bank)
15.1 CAS Latency = 2
15.2 CAS Latency = 3
16. Random Column Write ( Page within same Bank)
16.1 CAS Latency = 2
16.2 CAS Latency = 3
17. Random Row Read ( Interleaving Banks) with Precharge
17.1 CAS Latency = 2
17.2 CAS Latency = 3
18. Random Row Write ( Interleaving Banks) with Precharge
18.1 CAS Latency = 2
18.2 CAS Latency = 3
19. Precharge Termination of a Burst
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1. Bank Activate Command Cycle
2. Burst Read Operation
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3. Read Interrupted by a Read
4. Read to Write Interval
4.1 Read to Write Interval
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4. 2 Minimum Read to Write Interval
4. 3. Non-Minimum Read to Write Interval
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5. Burst Write Operation
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6. Write and Read Interrupt
6.1 Write Interrupted by a Write
6.2 Write Interrupted by a Read
