HYB39L128160AC-75 ,128-MBIT SYNCHRONOUS LOW-POWER DRAM
HYB39L128-160AC8 ,128-MBIT SYNCHRONOUS LOW-POWER DRAM
HYB39L128160AT-8 ,128-MBIT SYNCHRONOUS LOW-POWER DRAM
HYB39L128160AT-8 ,128-MBIT SYNCHRONOUS LOW-POWER DRAM
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HYB39L256160AC-8 ,256 MBit Synchronous Low-Power DRAMHYB39L256160AC/T256MBit 3.3V Mobile-RAM256 MBit Synchronous Low-Power DRAMData Sheet Revision Dec. ..
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ICT49FCT3805ASO , 3.3V CMOS BUFFER/CLOCK DRIVER
ICTE-18 ,Diode TVS Single Uni-Dir 18V 1.5KW 2-Pin Case 41A-04 Boxapplications0.210 (5.3) • High temperature soldering guaranteed:O0.190 (4.8) 265 C/10 seconds, 0.37 ..
HYB39L128160AC75-HYB39L128160AC-75-HYB39L128-160AC8-HYB39L128160AT-8
128-MBIT SYNCHRONOUS LOW-POWER DRAM
HYB39L128160AC/T
128-MBit 3.3V Mobile-RAMINFINEON Technologies12003-02
The HYB39L128160AC Mobile-RAM is a new generation of low power, four bank Synchronous
DRAM organized as 4 banks×2Mbit x16. These synchronous Mobile-RAMs achieve high speed
data transfer rates by employing a chip architecture that prefetches multiple bits and then
synchronizes the output data to a system clock.
All of the control, address, data input and output circuits are synchronized with the positive edge of
an externally supplied clock.
Operating the four memory banks in an interleave fashion allows random access operation to occur
at higher rate. A sequential and gapless data rate is possible depending on burst length, CAS
latency and speed grade of the device.
Auto Refresh (CBR) and Self Refresh operation are supported. The device operates with a single
3.3 V ± 0.3 V power supply.
Compared to conventional SDRAM the self-refresh current is further reduced. The Mobile-RAM
devices are available in FBGA “chip-size” or TSOPII packages.
High Performance:8Mbit x 16 organisationVDD = VDDQ = 3.3VFully Synchronous to Positive Clock EdgeFour Banks controlled by BA0 & BA1Programmable CAS Latency: 2, 3Programmable Wrap Sequence: Sequential
or InterleaveAutomatic and Controlled Precharge
CommandProgrammable Burst Length: 1, 2, 4, 8 and
full pageData Mask for byte controlAuto Refresh (CBR) 4096 Refresh Cycles / 64msVery low Self Refresh currentPower Down and Clock Suspend ModeRandom Column Address every CLK
(1-N Rule)54-FBGA , with 9 x 6 ball array with 3
depopulated rows, 9 x 8 mmOperating Temperature Range
Commerical (00 to 700C)
128-MBit Synchronous Low-Power DRAM
Datasheet (Rev. 2003-02)
HYB39L128160AC/T
128-MBit 3.3V Mobile-RAMINFINEON Technologies22003-02
Ordering Information
Pin Definitions and Functions
HYB39L128160AC/T
128-MBit 3.3V Mobile-RAMINFINEON Technologies32003-02
Pin Configuration for BGA devices:< Top-view >
123789ABCDEFGHJ
HYB39L128160AC/T
128-MBit 3.3V Mobile-RAMINFINEON Technologies42003-02
Pin Configuration for TSOP devices:
HYB39L128160AC/T
128-MBit 3.3V Mobile-RAMINFINEON Technologies52003-02
Functional Block Diagrams
Block Diagram: 8Mb x16 SDRAM (12 / 9 / 2 addressing)
