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HYB3117805BSJ-60
2M x 8 Bit 2k 3.3 V 50 ns EDO DRAM
SIEMENS
2M M 8-Bit Dynamic RAM
2k Refresh
(Hyper Page Mode-EDO)
Advanced Information
2 097 152 words by 8-bit organization
0 to 70 °C operating temperature
Hyper Page Mode-EDO-operation
HYB 5117805IBSJ-50l-60
HYB 3117805IBSJ-50l-60
Performance:
-50 -60
tRAC R/VS access time 50 60 ns
tCAC m access time 13 15 ns
tAA Access time from address 25 30 ns
tRC ReadNVrite cycle time 84 104 ns
tHPC Hyper page mode (EDO) cycle time 20 25 ns
Power dissipation:
HYB 5117805
HYB 3117805
-50 -60 -50 -60
Power Supply 5 i 10% 3.3 i 0.3 V
Active 440 385 288 252 mW
TTL Standby 11 7.2 mW
CMOS Standby 5.5 3.6 mW
Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh
and test mode
All inputs, outputs and clocks fully TTL (5 V versions) and LV-TTL (3.3 V version)-compatible
2048 refresh cycles / 32 ms (2k-refresh)
Plastic Package: P-SOJ-28-3 400 mil
Semiconductor Group
Sill EMENS HYB 5(3)117805/BSJ-5OI-60
2M x 8 EDO-DRAM
The HYB 5(3)117805 are 16 MBit dynamic RAMs based on the die revisions "G'' & "F'' and
organized as 2 097 152 words by 8-bits. The HYB 5(3)117805 utilizes a submicron CMOS silicon
gate process technology, as well as advanced circuit techniques to provide wide operating margins,
both internally and for the system user. Multiplexed address inputs permit the HYB 5(3)117805BJ
to be packaged in a standard SOJ-28 plastic packages. Package with 400 mil width are available.
These packages provide high system bit densities and are compatible with commonly used
automatic testing and insertion equipment.
Ordering Information
Type Ordering Code Package Descriptions
HYB 5117805BSJ-50 Q67100-Q1104 P-SOJ-28-3 400 mil 5 V 50 ns EDO-DRAM
HYB 5117805BSJ-60 Q67100-Q1105 P-SOJ-28-3 400 mil 5 V 60 ns EDO-DRAM
HYB 3117805BSJ-50 on request P-SOJ-28-3 400 mil 3.3 V 50 ns EDO-DRAM
HYB 3117805BSJ-60 on request P-SOJ-28-3 400 mil 3.3 V 60 ns EDO-DRAM
Pin Names and Configuration P-SOJ-28 400 mil
A0 - A10 Row Address Inputs
A0 - A9 Column Address Inputs VCCE IC) 28 II Vss
RAS Row Address Strobe I/O1E 2 27 II I/08
E Output Enable |/02 E 3 26 Ll IK)
I/O3 E 4 25 II |/06
l/OI - l/O8 Data Input/Output lK)4 E 5 24 Cl Q
CAS Column Address Strobe E E 6 23 II C_AS
W Read/Write Input RAS L 7 22 Ll OE
N.C. E 8 21 Cl A9
Vcc Power Supply A10 E q 20 1 A8
+5Vfor HYB 5117800 AOE10 19 IIA
+3.3VforHYB 3117805 A1E11 183%
VSS Ground (0 V) A2 E 12 17 Cl M
A3 C 13 16 Cl A4
N.C. Not Connected VCCE 14 15 II Vss
SPP02803
Semiconductor Group 2 1998-10-01
