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HYB3116405BT-60 |HYB3116405BT60HYN/a5704avai3.3V 4M x 4-Bit EDO-Dynamic RAM
HYB5117405BJ-60 |HYB5117405BJ60SIEMENSN/a29avai4M x 4-Bit Dynamic RAM 2k & 4k Refresh
HYB5117405BJ-60 |HYB5117405BJ60SMTN/a1012avai4M x 4-Bit Dynamic RAM 2k & 4k Refresh


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HYB3116405BT-60-HYB5117405BJ-60
4M x 4 Bit 4k 3.3 V 50 ns EDO DRAM
SIEMENS
4M M 4-Bit Dynamic RAM HYB 5116405BJ-50I-60
2k & 4k Refresh HYB 5117405BJ-50l-60
(Hyper Page Mode - EDO) HYB 3116405BJ/BT(L)-50/-60
HYB 3117405BJ/BT-50l-60
Advanced Information
4 194 304 words by 4-bit organization
. 0 to 70 °C operating temperature
. Hyper Page Mode - EDO - operation
. Performance:
-50 -60
tRAC RVs access time 50 60 ns
tCAC m access time 13 15 ns
tAA Access time from address 25 30 ns
tRC ReadNVrite cycle time 84 104 ns
tHPC Hyper page mode (EDO) cycle time 20 25 ns
. Power dissipation, refresh & addressing:
HYB 5116405 HYB 3116405 HYB 5117405 HYB 3117405
-50 -60 -50 -60 -50 -60 -50 -60
Powersupply 5V: 10% 3.31/t 0.3V 5V:10% 3.3V:0.3V
Addressing 12/10 12/10 11/11 11/11
Refresh 4096 cylces / 64 ms 2048 cycles / 32 ms
L-version 4096 cycles / 128 ms -
Active 275 220 180 144 440 385 288 252 mW
TTL Standby 11 7.2 11 7.2 mW
CMOS Standby 5.5 3.6 5.5 3.6 mW
CMOS Standby - 0.72 - - mW
(L-version)
. Read, write, read-modify-write, CAS-before-RAS refresh, RAS-only refresh, hidden refresh,
test mode and Self Refresh (on L-versions only)
. All inputs, outputs and clocks fully TTL (5 V versions) and LV-TTL (3.3 V version)-compatible
. Plastic Package: P-SOJ-26/24-1 300 mil
P-TSOPll-26/24-1 300 mil
Semiconductor Group 1 1998-10-01
Sill EM EN 5 HYB 5'rt6(7)405BJ-501-60
HYB 3116(7)405BJIBT(L)-50I-60
4M M 4 EDO-DRAM
The HYB 5(3)116(7)405 are 16 MBit dynamic RAMs based on die revisions "G" & "F'' and organized
as 4 194 304 words by 4-bits. The HYB 5(3)116(7)405BJ/BT(L) utilizes a submicron CMOS silicon
gate process technology, as well as advanced circuit techniques to provide wide operating margins,
both internally and for the system user. Multiplexed address inputs permit the HYB 5(3)116(7)405
to be packaged in a standard SOJ-26/24 and TSOPII-26/24 plastic package with 300 mil width.
These packages provide high system bit densities and are compatible with commonly used
automatic testing and insertion equipment. The HYB 3116(7)405BTL have a very low power "sleep
mode" supported by Self Refresh.
Ordering Information
Type Ordering Code Package Descriptions
2k-Refresh Versions:
HYB 5117405BJ-50 Q67100-Q1101 P-SOJ-26/24-1 300 mil 5 V 50 ns EDO-DRAM
HYB 5117405BJ-60 Q67100-Q1102 P-SOJ-26/24-1 300 mil 5 V 60 ns EDO-DRAM
HYB 3117405BJ-50 on request P-SOJ-26/24-1 300 mil 3.3 V 50 ns EDO-DRAM
HYB 3117405BJ-60 on request P-SOJ-26/24-1 300 mil 3.3 V 60 ns EDO-DRAM
HYB 3117405BT-50 on request P-TSOPll-26/24-1 300 mil 3.3 V 50 ns EDO-DRAM
HYB 3117405BT-60 on request P-TSOPll-26/24-1 300 mil 3.3 V 60 ns EDO-DRAM
4k-Refresh Versions:
HYB 5116405BJ-50 Q67100-Q1098 P-SOJ-26/24-1 300 mil 5 V 50 ns EDO-DRAM
HYB 5116405BJ-60 Q67100-Q1099 P-SOJ-26/24-1 300 mil 5 V 60 ns EDO-DRAM
HYB 3116405BJ-50 on request P-SOJ-26/24-1 300 mil 3.3 V 50 ns EDO-DRAM
HYB 3116405BJ-60 on request P-SOJ-26/24-1 300 mil 3.3 V 60 ns EDO-DRAM
HYB 3116405BT-50 on request P-TSOPll-26/24-1 300 mil 3.3 V 50 ns EDO-DRAM
HYB 3116405BT-60 on request P-TSOPll-26/24-1 300 mil 3.3 V 60 ns EDO-DRAM
HYB 3116405BTL-50 on request P-TSOPll-26/24-1 300 mil 3.3 V 50 ns LP-EDO-DRAM
HYB 3116405BTL-60 on request P-TSOPll-26/24-1 300 mil 3.3 V 60 ns LP-EDO-DRAM
Semiconductor Group 2 1998-10-01
ic,good price


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