HYB25L256160AC-7.5 ,Specialty DRAMsFeatures . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
HYB25L256160AC-7.5 ,Specialty DRAMsFunctional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ..
HYB25L256160AC-75 ,256-Mbit Mobile-RAMData Sheet, V1.1, April 2003HYB25L256160AC 256-Mbit Mobile-RAM2.5V VDDMemory ProductsNever stop t ..
HYB25L256160AF-7.5 ,Very low Power SDRAM optimized for battery-powered, handheld applicationsData Sheet, Rev. 1.3, Nov 2004HYB25L256160A[F/C]HYE25L256160AF 256MBit Mobile-RAM Mobile-RAM C ..
HYB25L512160AC ,512MBit Mobile-RAMData Sheet, Rev. 1.3, April 2004HYB25L512160AC–7.5 512MBit Mobile-RAM Standard Temp ..
HYB25L512160AC-7.5 ,Specialty DRAMsData Sheet, Rev. 1.2, Feb. 2004HYB25L512160AC–7.5HYE25L512160AC–7.5 512MBit Mobile-RAM ..
ICS9LPRS511EGLF , Low Power Programmable Timing Control Hub™ for P4™ processor
ICS9LPRS511EGLF , Low Power Programmable Timing Control Hub™ for P4™ processor
ICS9UMS9610CKLFT , PC MAIN CLOCK
ICSLV810FILFT , Buffer/Clock Driver
ICT49FCT3805ASO , 3.3V CMOS BUFFER/CLOCK DRIVER
ICTE-18 ,Diode TVS Single Uni-Dir 18V 1.5KW 2-Pin Case 41A-04 Boxapplications0.210 (5.3) • High temperature soldering guaranteed:O0.190 (4.8) 265 C/10 seconds, 0.37 ..
HYB25L256160AC-7.5
Specialty DRAMs
HYB25L256160AC
Revision History:2003-04-16V1.1
Previous Version:2001-11-23V1.0
Table of ContentsPageOverview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
PinConfiguration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6FunctionalDescription . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.1Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
3.2.1Burst Length . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3.2.2Burst Type . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.3Read Latency . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.2.4Operating Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
3.3Extended Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3.1Partial Array Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3.3.2Temperature Compensated Self Refresh with On-Chip Temperature Sensor . . . . . . . . . . . . . . . . 13
3.4Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.5Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
ElectricalCharacteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.1Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
4.2Timing Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
4.3Current Specification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
TimingDiagrams . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25PackageOutline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54
256-Mbit Mobile-RAM
Mobile-RAM
HYB25L256160AC
1Overview
1.1Features
16 Mbits × 16 organisationFully synchronous to positive clock edgeFour internal banks for concurrent operationData mask (DM) for byte control with write and read dataProgrammable CAS latency: 2 or 3Programmable burst length: 1, 2, 4, 8, or full pageProgrammable wrap sequence: sequential or interleavedRandom column address every clock cycle (1-N rule)Deep power down modeExtended mode register for Mobile-RAM featuresTemperature compensated self refresh with on-die temperature sensorPartial array self refreshPower down and clock suspend modeAutomatic and controlled precharge commandAuto refresh mode (CBR)8192 refresh cycles / 64 msSelf-refresh with programmble refresh periodProgrammable power reduction feature by partial array activation during self-refreshVDDQ = 1.8V or 2.5VVDD = 2.5V P-TFBGA-54 package 9-by-6-ball array with 3 depopulated rows (12 x 8 mm2)Operating temperature range: commerical (0°C to 70°C)
1.2Description
The 256-Mbit Mobile-RAM is a new generation of low power, four bank synchronous DRAM organized asbanksx4Mbitx16 with additional features for mobile applications. The synchronous Mobile-RAM achieves
high speed data transfer rates by employing a chip architecture that prefetches multiple bits and then synchronizes
the output data to a system clock.
The device adds new features to the industry standards set for synchronous DRAM products. Parts of the memory
array can be selected for Self-Refresh and the refresh period during Self-Refresh is programmable in 4 steps
which drastically reduces the self refresh current, depending on the case temperature of the components in the
Table1Performance1)for VDDQ = 2.5 V; see Table
10 for VDDQ dependent performance
Overview
interleave fashion allows random access operation to occur at higher rate. A sequential and gapless data rate is
possible depending on burst length, CAS latency and speed grade of the device.
The Mobile-RAM is housed in a FBGA “chip-size” package. The Mobile-RAM is available in the commerical (0°C
to 70°C) temperature range.
Table2Ordering InformationHYB/E: designator for memory components for commercial/extended temperature range
25L: Mobile-RAM at VDD = 2.5V
256: 256-Mbit density
160: Product variation x16
A: Die revision A
C: Package type FBGA
–7.5/8: speed grade - see Table
1
