HYB25D128323CL-4.5 ,128 Mbit DDR SGRAMData Sheet, V1.7, July 2003HYB25D128323C[-3/-3.3]HYB25D128323C[-3.6/L3.6]HYB25D128323C[-4.5/L4.5]HY ..
HYB25D128800CT-6 ,128 Mbit Double Data Rate SDRAMData Sheet, Rev. 1.0, Apr. 2004HYB25D128[400/800/160]C[C/E/T](L) 128 Mbit Double Data Rate SDRAM ..
HYB25D256160BT-5 ,DDR SDRAM Components HYB25D256[800/160]BT(L)-[5/5A]256MBit Double Data Rata SDRAMPreliminary DDR400 Data Sheet Addendum ..
HYB25D256160BT-6 ,DDR SDRAM Components HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. BData Sheet Jan. 2003, V ..
HYB25D256160BT-7 ,DDR SDRAM Components HYB25D256[400/800/160]B[T/C](L) 256-Mbit Double Data Rate SDRAM, Die Rev. BData Sheet Jan. 2003, V ..
HYB25D256160CC-6 ,DDR SDRAM ComponentsData Sheet, Rev. 1.11, Feb. 2004HYB25D256[40/80/16]0CE(L)HYB25D256[40/80/16]0C[C/F] 256 Mbit Double ..
ICS9DB306BLLFT , PCI Express, Jitter Attenuator
ICS9DB306BLLFT , PCI Express, Jitter Attenuator
ICS9DB401CFLFT , Four Output Differential Buffer for PCI Express
ICS9DB401CFLFT , Four Output Differential Buffer for PCI Express
ICS9DB801CFLFT , Eight Output Differential Buffer for PCI Express (50-200MHz)
ICS9LPRS511EGLF , Low Power Programmable Timing Control Hub™ for P4™ processor
HYB25D128323C-4.5-HYB25D128323C-45-HYB25D128323CL-4.5
128 Mbit DDR SGRAM
HYB25D128323C[-3/-3.3], HYB25D128323C[-3.6/L3.6], HYB25D128323C[-4.5/L4.5], HYB25D128323C-5
Revision History:V1.72003-07Previous Version:V1.512002-07
Previous Version:V1.512002-07
Overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91.1Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
1.2Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
3Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.1Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2Extended Mode Register Setup (EMRS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3Signal and Timing Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3.1General Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.4Special Signal Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.1Clock Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.2Command Inputs and Addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.3Data Strobe and Data Mask . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.3.1Operation at Burst Reads . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.4.3.2Operation at Burst Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5Description of Timings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5.1Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5.2Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5.3Extended Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.5.4Bank Activation Command (ACT) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5.5Precharge Command . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.5.6Self Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.5.7Auto Refresh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5.8Power Down Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.5.9Burst Mode Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.5.10Burst Read Operation: (READ) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.5.11Burst Write Operation (WRITE) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.5.12Burst Stop Command (BST) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
3.5.13Data Mask (DMx) Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
3.5.14Autoprecharge Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.5.15Read with Autoprecharge (READA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
3.5.16Write with Autoprecharge (WRITEA) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
3.6Burst Interruption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.6.1Read Interrupted by a Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
3.6.2Read Interrupted by a Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
3.6.3Read Interrupted by a Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.6.4Write Interrupted by a Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
3.6.5Write Interrupted by a Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.6.6Write Interrupted by a Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
3.7Operations and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
3.8Function Truth Tables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.9DDR SGRAM Simplified State Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
Table of Contents
Figure1Ball Out 128Mbit DDR SGRAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
Figure2Functional blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure3Mode Register Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
Figure4Extended Mode Register Bitmap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Figure5Command and Address Signal Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Figure6DQS Timing for Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Figure7DQS and DM Timing at Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure8DQS Pre/Postamble at Write . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure9Power-Up Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure10Mode Register Set Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
Figure11Activate to Read or Write Command Timing (one bank) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure12Activate Bank A to Activate Bank B Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
Figure13Precharge Command Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Figure14Self Refresh timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure15Autorefresh timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Figure16Power Down Mode timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Figure17Burst Read Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Figure18Burst Write Operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Figure19Burst Stop for Read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure20Data Mask Timing. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure21Read Burst with Autoprecharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure22Read Concurrent Auto Precharge . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Figure23Write Burst with Auto Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Figure24Read interrupted by Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure25Read interrupted by Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
Figure26Read interrupted by Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure27Write interrupted by Write. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33
Figure28Write interrupted by Read. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34
Figure29Write interrupted by Precharge. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Figure30DDR SGRAM Simplified State Diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
Figure31Output Test Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Figure32Package Outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52
List of Figures
Table1Performance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Table2Signal and Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
Table3IO Driver Strength and Interface Settings. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
Table4Mapping of DQSx and DMx . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
Table5Precharge Control. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table6Burst Mode and Sequence. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Table7Concurrent Read Auto Precharge Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table8Concurrent Write Auto Precharge Support. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Table9Command Overview. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Table10Abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table11Function Truth Table I. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
Table12Function Truth Table for CKE. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table13Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table14Power & DC Operation Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table15AC Operation Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table16Pin Capacitances . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43
Table17Timing Parameters for speed sorts –3, –3.3, –3.6, –4.5, and –5 . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Table18Timing Parameters for speed sorts L3.6 and L4.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46
Table19HYB25D128323C–3. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
Table20HYB25D128323C–3.3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table21HYB25D128323C–3.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table22HYB25D128323C–4.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table23HYB25D128323C–5. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49
Table24HYB25D128323CL3.6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table25HYB25D128323CL4.5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
Table26Operating Currents. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
List of Tables
128Mbit DDR SGRAM
HYB25D128323C[-3/-3.3]
HYB25D128323C[-3.6/L3.6]
HYB25D128323C[-4.5/L4.5]
HYB25D128323C-5
1Overview
1.1FeaturesMaximum clock frequency up to 333 MHzMaximum data rate up to 666 Mbps/pinData transfer on both edges of clockProgrammable CAS latency of 2, 3 and 4 clocksProgrammable burst length of 2, 4 and 8 Integrated DLL to align DQS and DQ transitions with CLKData transfer signals are synchronized with byte wise bidirectional Data StrobeData Strobe signal edge-aligned with data for Read operationsData Strobe signal center aligned with data for Write operationsDifferential clock inputs (CLK and CLK)Data mask for masking write data, one DM per byteOrganization 1024K×32×4 banks4096 rows and 256 columns per bank4K Refresh (32ms)Refresh Interval 7.8 µsecAutorefresh and Self Refresh availableStandard JEDEC TF-XBGA 128 packageSelf-mirrored, symmetrical ball outMatched Impedance Mode interface (Z0=60Ω)SSTL-2 JEDEC Weak Mode interface (Z0=34Ω)IO voltage VDDQ=2.5V VDD power supply memory core: Speed sorts –3 and –3.3: 2.5V < VDD < 2.9V Speed sorts L4.5, –4.5, and –5: VDD=2.5VSpeed sorts L3.6 and –3.6 support both VDD modes
1.2DescriptionThe Infineon 128Mbit DDR SGRAM is a ultra high performance graphics memory device, designed to meet all
requirements for high bandwidth intensive applications like PC graphics systems.
The 128Mbit DDR SGRAM uses a double-data-rate DRAM architecture organized as 4 banks×4096 rows×256
Table1Performance
OverviewSGRAM consists of a single 64-bit wide, one clock cycle data transfer at the internal DRAM core and two
corresponding 32-bit wide, one-half clock cycle data transfers at the I/O pins. The result is a data rate of 666 Mbits
/ sec per pin. The external data interface is 32 bit wide and achieves at 333 MHz system clock a peak bandwidth
of 2.66 Gigabytes/sec.
The device is supplied with 2.5V resp. within the range of 2.5V - 2.9V for the memory core and 2.5V for the
output drivers. Two drivers strengths are available: 2.5V Matched Impedance Mode and SSTL2 Weak Mode. The
“Matched Impedance Mode” interface is optimized for high frequency digital data transfers and matches the
impedance of graphics board systems (60Ohm).
Auto Refresh and Self Refresh operations are both supported.
A standard JEDEC TF-XBGA 128 package is used which enables ultra high speed clock and data transfer rates.
The signals are mapped symmetrically to the balls in order to enable mirrored mounting in application.
The chip is fabricated in Infineon technologies advanced 256M process technology.
Pin ConfigurationPin Configuration
Figure1Ball Out 128Mbit DDR SGRAMNote:The inner matrix of 4×4 balls will be used as thermal VSS contacts ncluding the thermal VSS contacts, the
total amount of balls is 144
Pin Configuration
Table2Signal and Pin Description
Pin Configuration
Table2Signal and Pin Description (cont’d)
Pin Configuration
Figure2Functional blocks
Register Set
3Register Set
3.1Mode RegisterThe mode register stores the data for controlling the various operating modes of the DDR SGRAM. It programs
CAS latency, addressing mode, burst length, test mode, DLL ON and various vendor specific options. The default
value of the mode register is not defined. Therefore the mode register must be written after power up to operate
the DDR SGRAM. The DDR SGRAM should be activated with CKE already high prior to writing into the Mode
Register. The Mode Register is written by using the MRS command. The state of the address signals registered
in the same cycle as MRS command is written in the mode register. The value can be changed as long as all banks
are in the idle state.
The mode register is divided into various fields depending on functionality. The burst length uses A2.. A0, CAS
latency (read latency from column address) uses A6.. A4. A7 is used for test mode, A8 is used for DLL Reset. A7,
A8 and BA1 must be set to low for normal DDR SGRAM operation. A9.. A11 is reserved for future use. BA0 selects
Extended Mode Register Setup operation when set to 1. Refer to the table for specific codes for various burst
length, addressing modes and CAS latencies.
Figure3Mode Register Bitmap
Register Set
3.2Extended Mode Register Setup (EMRS)The Extended Mode Register is responsible for enabling / disabling the DLL in the HYB25D128323C and for
selecting the interface type for the IOs and input pins. The Extended Mode Register can be programmed by
performing a normal Mode Register Setup operation and setting the BA0 bit to high. All other bits of the EMRS
register are reserved and should be set to low.
The Bit A0 enables / disables the DLL.
The Bits A1 and A6 set the driver strength of the IOs. For detailed explanation, refer to the following table.
Note:The combination A6=0 and A1=0 defines SSTL-2 strong mode in 32M DDR SGRAM which is not supported
in this device.
Figure4Extended Mode Register Bitmap
3.3Signal and Timing Description
3.3.1General DescriptionThe 128Mbit DDR SGRAM is a 16MByte Synchronous Graphics DRAM. It consists of four banks. Each bank is
organized as 4096 rows×256 columns×32 bits.
Read and Write accesses are burst oriented. Accesses begin with the registration of an Activate command, which
is then followed by a Read or Write command. The address bits registered coincident with the Activate command
are used to select the bank and the row to be accessed. BA1 and BA0 select the bank, address bits A11.. A0 select
the row. Address bits A7.. A0 registered coincident with the Read or Write command are used to select the starting
column location for the burst access.
Table3IO Driver Strength and Interface Settings
Register Setread bursts, the data valid window coincides with the high or low level of the DQSx signals. During write bursts,
the DQSx signal marks the center of the valid data window. Data is available at every rising and falling edge of
DQSx, therefore the data transfer rate is doubled.
For Read accesses, the DQSx signals are aligned to the clock signal CLK.
3.4Special Signal Description
3.4.1Clock SignalThe DDR SGRAM operates with a differential clock (CLK and CLK#) input. CLK is used to latch the address and
command signals. Data input and DMx signals are latched with DQSx. The DDR SGRAM implements a Delay
Locked Loop circuit (DLL) which tracks both edges of the CLK input signal and aligns the DQS output edges with
the CLK input edges.
The minimum and maximum clock cycle time is defined by tCK. The maximum value for tCK is defined to provide a
lower bound for the operation frequency of the internal DLL circuit. The minimum and maximum clock duty cycle
are specified using the minimum clock high time tCH and the minimum clock low time tCL respectively.
The internal DLL circuit requires additional 200 clock cycles after DLL reset for internal clock stabilization.
3.4.2Command Inputs and AddressesLike single data rate SGRAMs, each combination of RAS#, CAS# and WE# input in conjunction with CS# input at
a rising edge of the clock determines a DDR SGRAM command.
Figure5Command and Address Signal Timing
3.4.3Data Strobe and Data Mask
3.4.3.1Operation at Burst ReadsThe Data Strobes provide a 3-state output signal to the receiver circuits of the controller during a read burst. The
data strobe signal goes tRPRE clock cycle low before data is driven by the DDR SGRAM and then toggles low to
high and high to low till the end of the burst. The CAS latency is specified to the first low to high transition. The
edges of the Output Data signals and the edges of the data strobe signals during a read are nominally coincident
with edges of the input clock. The tolerance of these edges is specified by the parameters tAC and tDQSCK and is
referenced to the crossing point of the CLK and CLK# signal. The tDQSQ timing parameter describes the skew
between the data strobe edge and the output data edge.
Register SetThe minimum time during which the output data is valid is critical for the receiving device. This also applies to the
Data Strobe DQS during a read since it is tightly coupled to the output data. The parameters tQH and tDQSQ define
the minimum output data valid window.
Prior to a burst of read data, given that the device is not currently in burst read mode, the data strobe signals transit
from Hi-Z to a valid logic low. This is referred to as the data strobe “read preamble” tRPRE.
Once the burst of read data is concluded, given that no subsequent burst read operation is initiated, the data strobe
signals transit from a valid logic low to Hi-Z. This is referred to as the data strobe “read postamble” tRPST.
Figure6DQS Timing for Read
3.4.3.2Operation at Burst WriteDuring a write burst, control of the data strobe is driven by the memory controller. The DQSx signals are nominally
centered with respect to data and data mask. The tolerance of the data and data mask edges versus the data
strobe edges during writes are specified by the setup and hold time parameters of data (tQDQSS & tQDQSH) and data
mask (tDMDQSS & tDMDQSH). The input data is masked in the same cycle when the corresponding DMx signal is high
(i.e. the DMx mask to write latency is zero.)
Table4Mapping of DQSx and DMx
Register Set
Figure7DQS and DM Timing at WritePrior to a burst of write data, given that the controller is not currently in burst write mode, the data strobe signal
(DQSx) transits from Hi-Z to a valid logic low. This is referred to as the data strobe “Write Preamble”. Once the
burst of write data is concluded, given that no subsequent burst write operation is initiated, the data strobe signal
(DQSx) transits from a valid logic low to Hi-Z. This is referred to as the data strobe “Write Postamble”, tWPST. For
DDR SGRAM, data is written with a delay which is defined by the parameter tDQSS (DDR write latency). This is
different than the single data rate SGRAM where data is written in the same cycle as the Write command is issued.
Figure8DQS Pre/Postamble at Write
Register Set
3.5Description of Timings
3.5.1Power-Up SequenceThe following sequence is highly recommended for Power-Up:Apply power and start clock. Maintain CKE=L and the other pins are in NOP conditions at the inputApply VDD before or at the same time as VDDQ, apply VDDQ before or at the same time as VREF & VTT3.Start clock, maintain stable conditions for 200 µs min.Apply NOP and set CKE to highApply a Precharge All commandIssue EMRS (extended mode register set) command to enable the DLLIssue a Mode Register Set command for “DLL reset“. 200 cycles of clock input are required to lock the DLL.Issue Precharge commands for all banks of the device.Issue two or more Auto-Refresh commands.
10.Issue a Mode Register Set command. (This step may also be taken as step 6)
Figure9Power-Up Sequence
3.5.2Mode Register Set TimingThe DDR SGRAM should be activated with CKE already high prior to writing into the mode register. Two clock
cycles are required to complete the write operation in the mode register. The mode register contents can be
changed using the same command and clock cycle requirements during operation as long as all banks are in the
idle state.
Figure10Mode Register Set Timing
3.5.3Extended Mode Register Set TimingThe timing of the Extended Mode Register Setup operation is equivalent to the Mode Register Setup timing.
Register Set
3.5.4Bank Activation Command (ACT)The Bank Activation command is initiated by issuing an ACT command at the rising edge of the clock. The DDR
SGRAM has four independent banks which are selected by the two Bank select Addresses (BA0, BA1). The Bank
Activation command must be applied before any Read or Write operation can be executed. The delay from the
Bank Activation command to the first read or write command must meet or exceed the minimum of RAS to CAS
delay time (tRCDDC min. for read commands and tRCDWR min. for write commands). Once a bank has been activated,
it must be precharged before another Bank Activate command can be applied to the same bank. The minimum
time interval between interleaved Bank Activate commands (Bank A to Bank B and vice versa) is the Bank to Bank
activation delay time (tRRD min).
Figure11Activate to Read or Write Command Timing (one bank)
Figure12Activate Bank A to Activate Bank B Timing
3.5.5Precharge CommandThis command is used to precharge or close a bank that has been activated. Precharge is initiated by issuing a
Precharge command at the rising edge of the clock. The Precharge command can be used to precharge each
bank respectively or all banks simultaneously. The Bank addresses BA0 and BA1 select the bank to be
precharged. After a Precharge command, the analog delay tRP has to be met until a new Activate command can
be initiated to the same bank.
Register Set
Figure13Precharge Command Timing
3.5.6Self RefreshThe self refresh mode can be used to retain the data in the DDR SGRAM if the chip is powered down. To set the
DDR SGRAM into a self refreshing mode, a Self Refresh command must be issued and CKE held low at the rising
edge of the clock. Once the self Refresh command is initiated, CKE must stay low to keep the device in Self
Refresh mode. During the Self refresh mode, all of the external control signals are disabled except CKE. The clock
is internally disabled during Self Refresh operation to reduce power. An internal timing generator guarantees the
self refreshing of the memory content. To exit the Self Refresh mode, a stable external clock is needed for the DLL
before returning CKE high. After the Power Down Exit time(tPDEX), a Deselect or NOP command is issued and CKE
is held high for longer than tSREX in order to lock the DLL.
Table5Precharge Control
Register Set
Figure14Self Refresh timing
3.5.7Auto RefreshThe auto refresh function is initiated by issuing an Auto Refresh command at the rising edge of the clock. All banks
must be precharged and idle before the Auto Refresh command is applied. No control of the external address pins
is required once this cycle has started. All necessary addresses are generated in the device itself. When the
refresh cycle has completed, all banks will be in the idle state. A delay between the Auto Refresh command and
the next Activate Command or subsequent Auto Refresh Command must be greater than or equal to the tRFC(min).
Figure15Autorefresh timing
3.5.8Power Down ModeThe Power Down Mode is entered when CKE is set low and exited when CKE is set high. The CKE signal is
sampled at the rising edge of the clock. Once the Power Down Mode is initiated, all of the receiver circuits except
CLK, CKE and DLL circuits are gated off to reduce power consumption. All banks can be set to idle state or stay
activate during Power Down Mode, but burst activity may not be performed. After exiting from Power Down Mode,
at least one clock cycle of command delay must be inserted before starting a new command. During Power Down
Mode, refresh operations cannot be performed; therefore, the device cannot remain in Power Down Mode longer
than the refresh period (tREF) of the device.
Register Set
Figure16Power Down Mode timing
3.5.9Burst Mode OperationBurst mode operation is used to provide a constant flow of data to the memory (write cycle) or from the memory
(read cycle). The burst length is programmable and set by address bits A0 - A3 during the Mode Register Setup
command. The burst length controls the number of words that will be output after a read command or the number
of words to be input after a write command. One word is 32 bits wide. The sequential burst length can be set to 2,
4 or 8 data words.
3.5.10Burst Read Operation: (READ)The Burst Read operation is initiated by issuing a READ command at the rising edge of the clock after tRCD from
the bank activation. The address inputs (A7.. A0) determine the starting address for the burst. The burst length (2,
4 or 8) must be defined in the Mode Register. The first data after the READ command is available depending on
Table6Burst Mode and Sequence
Register Set
Figure17Burst Read Operation
3.5.11Burst Write Operation (WRITE)The Burst Write is initiated by issuing a WRITE command at the rising edge of the clock. The address inputs (A7..
A0) determine the starting column address. Data for the first burst write cycle must be applied on the DQ pins on
the first rising edge of DQSx following the WRITE command. The time between the WRITE command and the first
corresponding edge of the data strobe is tDQSS. The remaining data inputs must be supplied on each subsequent
rising and falling edge of the data strobe until the burst length is completed. When the burst has been finished,
any additional data supplied to the DQ pins will be ignored.
Register Set
Figure18Burst Write Operation
3.5.12Burst Stop Command (BST)A Burst Stop is initiated by issuing a BURST STOP command at the rising edge of the clock. The Burst Stop
Command has the fewest restrictions, making it the easiest method to terminate a burst operation before it has
been completed. When the Burst Stop Command is issued during a burst read cycle, read data and DQSx go to
a high impedance state after a delay which is equal to the CAS Latency set in the Mode Register. The Burst Stop
latency is equal to the CAS latency CL.The Burst Stop command is not supported during a write burst operation.
Burst Stop is also illegal during Read with Auto-Precharge.
Register Set
Figure19Burst Stop for Read
3.5.13Data Mask (DMx) FunctionThe DDR SGRAM has a Data Mask function that can be used only during write cycles. When the Data Mask is
activated (DMx high) during burst write, the write operation is masked immediately. The DMx to data-mask latency
is zero. DMx can be issued at the rising or falling edge of Data Strobe.
