HPC36400EV20-HPC46400EV20 Fast Delivery |IC PHOENIX CO.,LIMITED

HPC46400EV20 ,20 MHz, 100 mA, 7 V, high-performance communication microcontrollerapplications - Programmable frame address recognition - Up to 4.65 Mbps serial data rate - Built ..
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HPC36400EV20-HPC46400EV20
20 MHz, 100 mA, 7 V, high-performance communication microcontroller
National
Semiconductor
PRELIMINARY
HPC16400E/HP036400E/HPC46400E
High-Performance Communications microcontroller
General Description
The HPC 16400E is an upgraded HPC 16400. Features have
been added to support V. Mo, the 8-bit mode has been en-
hanced to support all instructions, and the UART has been
changed to provide more flexibility and power. Tha
HPC16400E is fully upward compatible with the HPC 16400.
The HPC16400E has 4 functional blocks to support a wide
range of communication application-2 HDLC channels, 4
channel DMA controller to facilitate data flow for the HDLC
channels, programmable serial interface and UART.
The serial interface decoder allows the 2 HDLC channels to
be used with devices using interchip serial link for point-to-
point and multipoint data exchanges. The decoder gener-
ates enable signals for the HDLC channels allowing multi-
plexed D and B channel data to be accessed.
The HDLC channels manage the link by providing sequenc-
ing using the HDLC framing along with error control based
upon a cyclic redundancy check (CRC). Multiple address
recognition modes, and both bit and byte modes of opera-
tion are supported.
The HPC16400E is available in 68-pin PLCC. LDCC, PGA
and 84-Pin TapePakO packages.
Features
rt HPCTM family-core features:
- 16-bit data bus, ALU, and registers
- 64 kbytes of external memory addressing
- FASTi--20,0 MHz system ciock
- Four 16-bit timer/counters with WATCHDOG logic
- MlCROWlRE/PLUSTM serial I/O interface
- CMOS-low power with two power save modes
a Two full duplex HDLC channels
- Optimized for ISDN, X.25, v.120, and LAPD
applications
- Programmable frame address recognition
- Up to 4.65 Mbps serial data rate
- Built in diagnostics
- Synchronous bypass mode
- Optional CRC generation
- Received CRC bytes can be read by the CPU
It Four channel DMA controller
a 8- or 16-bit external data bus
gt UART
- F ull duplex
- 7, 8, or 9 data bits
- Even, odd, mark, space or no parity
- 7/8, 1 or 2 stop bit generation
-Atxturate internal baud rate generation up to 625k
baud without penalty of using expensive crystal
- Synchronous and asynchronous modes of operation
rt Serial Decoder
-Supports 6 popular time division multiplexing proto-
cols for inter-chip communications
-Optional rate adaptation of 64 kbit/s data rate to
56 kbit/s
u Over y, Mbyte of extended addressing
1: Easy interface to National's DASL. 'U' and 'S' trans-
ctrivers-TP3400, TP3410 and TP3420
a Commercial (tPC to + 70°C), industrial (-4C'C to
+85''C) and military (-55'C to +125°C) temperature
ranges
ce, Tm um nmI/rs/an REM/RHCKZ
P"-"e...e"_".e"""""""""V .............. . " um um um m
Pl' HLD nzsn' sums we on cxo Tl me my TD" m rm
' t I I
I l l t t I , , "I l l
mrcuuoc
I LOGIC cuxtd I UH" HDLC n HDLC "
I I MEX/RtG I A
I LOGC m , w , d k n
I W05 I
s ChrT1lttt sum
I REGISTERS mun I 2M nu “mom 4 mm M
I _ HALT I n "
' t 1 AXE ' t
I r l " w 7 i, , I r
t " I g A " d I I I d
' cw nmsm ,
' (t6 m 1 6-3” I l I , I r /
- A - ADDR/ uuxzn Mum
I - a - " t MN1S am l/O l 'tul''' INPUTS
I - x - unnowmz/ t
I hUl rwsm I
I - It - I
I 111:
l - " - K: PORTI PORTB PORTD
l ammo: I
l not: con: CPU I
TL/DD/10422-I
300V9V0dH/EOOV980dH/300V9LOdH
HPC16400E/HPC36400E/HPC46400E
Absolute Maximum Ratings
If MllltaryfAeroapaee specified devices are required,
please contact the National Sttrttittttrtdutttor Sales
offltte/DIBtrltttttors for avaliablllty and specifications.
Total Allowable Source or Sink Current 100 mA
Storage Temperature Range -65'C to + 150'C
Lead Temperature (Soldering, 10 sec.) 300'C
ESD Rating is to be determined
Vcc with Respect to GND --0.5V to 7.0V
All Other Pins (Vcc + 0.5)V to (GND - 0.5)V
Note: Absolute maximum ratings indicate limits beyond
which damage to the device may occur. 00 and AC tgtttttti-
cal speeifieations are not ensured when operating the de-
vice at absolute maximum ratings.
DC Electrical Characteristics voc = 5.0V i10% unless otherwise specified, TA = 0% to +70% for
HPC46400E. - 40°C to + 85'C for HPC36400E, - 55°C to + 125°C for HPC16400E
Symbol Parameter Test Conditions Min Max Units
ICC, Supply Current Vcc = 5.5V,fin = 20.0 MHz (Note 1) 70 mA
vcc = 5.5V,tin = 2.0 MHz (Note 1) 10 mA
'062 IDLE Mode Current Vcc = 5.5V, fin = 20.0 MHz (Note I) 10 mA
Vcc = s.sv, fin = 2.0 MHz (Note 1) 2 mA
Ices HALT Mode Current vcc = 5.5V, fin = 0 kHz (Note I) 500 “A
Vcc = 2.5V, tin = 0 kHz (Note 1) 150 p.A
INPUT VOLTAGE LEVELS-SCHMiTT TRIGGERED: RESET, CKI, W0, DO, l1, l2, l3
V1111 Logic High 0.9 Vcc v
VIL1 Logic Low 0.1 Vcc v
INPUT VOLTAGE LEVELS-PORT A
V1112 Logic High 2.0 v
Vng Logic Low 0.8 V
INPUT VOLTAGE LEVELS-ALL OTHERS
V1113 Logic High 0.7 vcc v
Vita Logic Low 0.2 vcc v
L Input Leakage Current (Note 2) AI ”A
Q Input Capacitance (Note 3) 10 pF
tho I/O Capacitance (Note 3) 20 pF
OUTPUT VOLTAGE LEVELS
V0111 Logic High (CMOS) km = - 10 11A (Note a) vcc - 0.1 v
VOL, Logic Low (CMOS) 10H = 10 “A (Note 3) 0.1 v
Wore Port A/B Drive, CK2 10H = -7 mA 2.4 v
V0L2 (AO-AIS, BIO, B11. Be, BIS) lot. = 3 mA 0.4 V
VOH3 Other Port Pin Drive, W6 (open drain) IOH = - 1.6 mA (except m) 2.4 V
VOL3 (Btr-Bi,B14,Ro-Rr,ths,Dr) IOL = 0.5 mA 0.4 v
V0144 ST1 and ST2 Drive 10... = -6 mA 2.4 v
V014 lot. = 1.6 mA (Note 4) 0.4 V
VRAM RAM Keep-Ative Voltage (Note 5) 2.5 V
loz TRI-STATE Leakage Current i 5 pA
Note 1: loc1. loge. Ictk, measured with no external drive (IOH and IOL '= o, IIH and kt. == 0). lcc, Is measured with WES? = vss, logs is measured with NMI =
Vcc. CKI driven to VIH1 and V.L1 with rise and fall times less than 10 na.
Note 2: WNW and WIN pins have internal pullups and meet this spec only at VIN = Vcc.
Note 3: These parameters are guaranteed by design and are not tested.
Note 4: 8T2 drive will not meet this spec undel condition tat RESET pin = low.
Note S: Test duration is 100 ms.
AC Electrical Characteristics
(see Notes 1 and 4 and Figures 1 thru 5), Vcc = 5V 110%. TA == ty'C to +70°C for HPC46400E. -40''C to +85°C for
HPC36400E, -55t to + 125°C for HPC16400E
Symbol and Formula Parameter and Notes Min Max Units Note
to CKI Operating Frequency 2 20 MHz
ttM = 1/1c CKI Period 50 500 ns
tan CKI Rise Time 7 ns (Note I)
t01F CKI Fall Time 7 ns (Note 1)
100 tc1H/tc1 CKI Duty Cycle 45 55 M, (Note I)
to = 2/10 CPU or DMA Timing Cycle 100 ns
g tWAIT = to CPU or DMA Wait State Period 100 ns
- 109102;; Delay of CK2 Rising Edge after
0 CKI Falling Edge 0 55 ns (Note 2)
tDC1CZF Delay of CK2 Falling Edge after
CKI Falling Edge 0 55 ns (Note 2)
fu = tc/8 External UAHT Clock Input F requency 2.5 MHz
wa = tel 19 External MlCROWIFtE/PLUS 1 25 MHz
Clock Input Frequency _
tHCK = 4tc1 + 14 HDLC Clock Input Period 214 ns
E fxm = tc/19 External Timer Input Frequency 1052 kHz
g txm = tt Pulse Width for Timer Inputs 100 ns
F fXOUT = tel 16 TimerOutput Frequency 1.25 MHz
a tuws MICROWIRE Setup Time-- Master 100 ns
JI - Slave 20 ns
it tum, MICROWIRE Hold Time-- Master 20 ns
E - Slave 50 ns
ks" tuwv MICROWIRE Output Valid Time - Master 50 ns
E - Slave 1 50 ns
E tSALE = % to + 40 HLD Falling Edge before ALE Rising Edge 115 ns
g ’1pr = % tC + 85 HLD Pulse Width 110 ns
a tHAE = y. tt + 100 HLDA Falling Edge after HLD Falling Edge 175 ns (Note 3)
E tHAD = s/ttc + M HEDA Rising Edge after HLD Rising Edge 210 ns
h' tap Bus Float after HLDA Falling Edge 66 ns
IU tag = to -- 66 Bus Enable after HLDA Rising Edge 34 ns
Note 1: These AC characteristics are guaranteed with external clock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO. Spec'd 1cm. ttlr,
and CKI duty cycle limits are not tested but are guaranteed functional by design.
Natl 2: Do not design with this parameter unless CKI is diven with an active signal meeting Tam and Tc“: specs. When using a passive crystal circuit. its stability
is not guaranteed if either CKI or CKO is eonnacted to any external logic other than the passive components of the crystal circuit.
Note a: tHAE is spec'd for case with mm tailing edge occuning at the latest time it can be accepted during the present CPU or DMA cycle being executed. lf m
falling edge occurs later, tHAE as long as (a ta + 4 WS + 72 to + 100) may occur depending on the following CPU instruction or DMA cycle, its wait states and
ready input
Note 4: WS (MAW) X (number of preprogrammed wait states). Minimum and maximum values are catculated at maximum operating frequency, to = 20 MHz. with
one wait state pttrprogr8mrmsd. These values are guaranteed with AG loading of 100 pF on Port A, 50 pF on oe, 80 pF on other outputs, and DC loading of the
pin's DC spec non CMOS IOL or km,
HOOPSVGdH/EOOVQSOdI-l[300WLOdH
HPC16400E/HPC364OOE/HPC464OOE
AC Electrical Characteristics (Continued)
CPU and DMA Timing (see Notes 1 and 4 and Figures 2, 4, 6, F, 8, and 9), Vcc = 5V i10%, TA = 0°C to +70''C for
HPC46400E, --4ty'C to +85'C for HPC36400E, -55°C to + 125°C for HPC16400E
Symbol Formula Cycle Parameter Mln Max Units Note
tum CPU Delay of ALE Rising Edge after CKI Rising Edge 0 35 ns (Note 2)
DMA Delay of ALE Rising Edge after CKI Falling Edge 0 35 ns (Note 2)
3 ttALF CPU Delay of ALE Falling Edge after CKI Rising Edge 0 35 ns (Note 2)
Ta DMA Delay of ALE Falling Edge after CKI Falling Edge 0 35 ns (Note 2)
g tzALR 1/410 + 20 CPU ALE Rising Edge after CK2 Rising Edge 45 ns
tl taALF Ye tt + 20 CPU ALE Falling Edge after CK2 Falling Edge 45 ns
3 tLL V2 tc _ 9 ALE Pulse Width 41 ns
tsr 'A tt - 16 Setup of Address Valid before ALE Falling Edge 9 ns
M: l/a to _ 10 CPU Hold of Address Vaiid after ALE Falling Edge 15 ns
y, to - 10 DMA 40 ns
tAFlR y, to - 20 ALE Falling Edge to W Falling Edge 30 ns
tACC to + WS - 55 CPU Data Input Valid after Address Output Valid 145 ns
ze + WS - 75 DMA 150 ns
' tRD 1/4 to + WS - 35 CPU Data Input Valid attsrAT Falling Edge 90 ns
Ti V, tc + WS DMA 115 ns
g tRw 'Att + ws - 10 CPU H_D Pulse Width 115 ns
g 'Att; + WS - 15 DMA 135 ns
a km tt - 15 CPU Hold ot Data IrtputValid after AU Rising Edge 0 M ns (Note 5)
3/. tc - 15 DMA 0 60 ns (Note 5)
tRDA tc - 5 CPU Bus Enable atterFTU Rising Edge 95 ns (Note 5)
14 tc - 5 DMA 70 ns (Note 5)
a tARw y, to - 20 ALE Falling Edge to WA Falling Edge 30 ns
' tww % tt+WS - 15 GPU WA- Pulse Width 160 ns
5' 'htc+WS - 15 DMA 135 ns
g tv y, to + ws _ 40 CPU Data Output Valid before WA Rising Edge 1 10 ns
3 1/213 + ws _ 50 DMA 100 ns
tHW l/e to - 10 Hold of Data Output Valid after W Rising Edge 15 ns
= tRDys ABT Falling Edge before CK2 Rising Edge 45 ns
E il tRDYH RDY Rising Edge after CK2 Rising Edge 0 ns
rt -- -
n: - tnovv WS - V4 tc - 47 CPU RDY Falling Edge after RD orWA Falling Edge 28 ns (Note 6)
lg - 47 DMA 53 ns
Note 1: These AC characteristics are guaranteed with Meme} cIock drive on CKI having 50% duty cycle and with less than 15 pF load on CKO. Spec'd tclit, 101p.
and CKI duty cycle limits are not tested but are guaranteed functional by design.
Note 2: Do not design with this parameter unless CKI is driven with an active signal meeting Tom and TCIF specs. When using a passive crystal circuit. its stability
Is not guaranteed it either CKI or CKO Is connected to any external logic other than the passive components of the crystal circuit.
Note 31‘HAE ls spec'd for case with WED falling edge occurring at the latest time it can be accepted during the present CPU or DMA cycle being executed. If WED
talllng edge occurs later, ‘HAE " tong as (3 tc + 4 WS + 72 to + 100) may occur depending on the1ollowing CPU instruction or DMA cycle, its wait states and
ready Input.
Note 4: WS (twmr) x (number of pmprograrsned watt states). Minimum and maximum values are calculated at maximum operating frequency, fc - 20 MHz, with
one wait state prepmgrarnrmxi. These values are guaranteed with AC loading of 100 pF on Port A, 50 pF on CK2, so pF on other outputs, and DC loading of the
pln's DC spec non CMOS lor. or [01.1.
Note 6: Formula has 7/. to for CPU read followed by DMA % to for DMA read followed by CPU.
Note a: In HPC in-circuit emulator: the ttttrw formulas are WS - V. to - 57 and k: - 57 yielding mlnlmums of 18 ns and 43 ns for CPU and DMA cycles.
respectively.
Timing Waveforms
Hlse/Fall Time Duty Cycle
CKI CKI 50%
tcm tcu
TL/DD/10422-2 k,
FIGURE 1. CKI Input Signal
IH V v
2" TEST POINTS VOH
V OL 0L
IL TL/DD/10422-4
Note: AC testing inputs are driven at V.” for a logic "1" and W. fora logic "ty'. Output timing measuemems are made at VOH for a logic "1" hoid or rising edge and
at Vac for a logic "o" hold or falling edge.
‘cm tcts
TLIDD/10422-3
FIGURE 2. Input and Output for AC Tests
l--------?-------!
st-f""'-,',-..,...,.,...,,."
Sl "j? I' x
FIGURE 3. MICROWIRE Setup/Hold Timing
TLahht0422-5
k I ia '
CKI -si-,/---i-sr------ic.-j')-i-
ttmeat ‘nctczr
CK2 _/ 'c-.......,...,.,.-,?'').
tout ttur
ALE FOR f ,
CPO CYCLE I k
tout HALF
ALE FOR
Mth CYCLE -- mu
TL/DDf10422-6
FIGURE 4. CKI, CK2 ALE Tlmlng Dlagram
ALE TRhSTATE r-l i--'l
F-tsau -/
F-u, -+-too -/
‘HA: *I - tas
PERTA TRl-STATE m
ME, Bo, wn "W
FIGURE 5. External Hold Tlmlng
TL/DDf10422-7
3007970dH/3007980dHIEOO‘PQlOdH
HPC16400E/HPC36400E/HPC46400E
Timing Waveforms (Continued)
u _ _ tom -
m k, /-''"'Ac.,.....
ttt - ter-d
NIT l W mlt I ( MM Wt VALID F-t Mott MIT
I N l, W
um t i
FIGURE 6. CPU and DMA Write Cycles
u '11:
ALE _)"""''"),
ts, trr
NIT. -----_ AIMDUT
TL/DD/10422-B
DATA m VALID H Mott BUT
TL/DDI 10422- 9
FIGURE 7. CPU and DMA Read Cycles
F-tA-)------)------!
--l--! ‘aom
ALE i-
tiow F-l
E on vTR I
if): VTR
Tt.2 DD/1 0422- 10
FIGURE 8. CPU Ready Made with 1 Walt State and Ready Walt Extension
1---u--+-m---+-m-+-s--+--o--l
tems '
tavwr----/
it7r0tt% I
--l-y''m
TL/DD/10422-11
FIGURE 9. DMA Ready Mode with 2 Walt States and Ready Walt Extension
2-1 34
Timing Waveforms (Continued)
Tlmlng Diagrams for TX Uslng External Enable
'i,', ri) M "n--"''""""--""'''"-'''''''')'-'',','')?,,-,
m ts,, m y"'---
(outpug arr: X an: x 3m x ens X Bits fem} arr'y
-4 TVTE - TVTC m: -l -
TL/DD/10422-12
Symbol Parameter Min Max Units
TETE Hold of TEN Low after HCK Rising Edge 5 ns
TLTE Setup of TEN Rising Edge before HCK Rising Edge 80 ns
TVTE Delay of TX Output Valid after TEN Rising Edge 40 ns
TVTC Delay of TX Output Valid after HCK Rising Edge 45 ns
THTE Hold of TEN High after HCK Falling Edge 60 ns
TSTE Setup of TEN Falling Edge before HCK Falling Edge 20 ns
TITE Delay of TX Output TRI-STAT? after TEN Falling Edge , 40 ns
Timing Diagrams for RX Using External Enable
(mnmng); X cm X m2 m4 X Btts {am X am x wax X
TL/DDI10422-13
Symbol Parameter Min Max Units
TERE Hold of REN Low after HCK Rising Edge 5 ns
TLRE Setup of REN Rising Edge before HCK Falling Edge 30 ns
TVRS Setup of RX Data Input Valid before HCK Falling Edge 20 ns
TVRH Hold ot RX Data Input Valid after HCK Falling Edge 20 ns
THRE Hold of REN High after HCK Rising Edge 5 ns
TSRE Setup of REN Falling Edge before HCK Falling Edge 30 ns
HOOVSVOdH/HOMQEQdHIEOO‘PSlOdH
HPC16400E/HPC36400E/HPC46400E
Timing Waveforms (Continued)
Serial Decoder Tlmlng Diagram (Mode 2)
mm ld I E'"" I 33rd 34th -
HCK1 Hem
rs N, h (M "
= Pm Tus- jmrs
- TSFS
(WWI) wrc - - - V we
TLIDD/10422-14
Symbol Parameter Mln Max Comments Units
TPFS Number of HCK1 Periods between FS Falling Edges 34
TAFS Number of HCK1 Rising Edges during FS Low 1 32
TEFS Hold of FS High after HCK1 Rising Edge 10 Early FS ns
TLFS Setup of FS Falling Edge before HCK1 Rising Edge 20 Late FS, (Note 8) ns
TVFC Delay of TX Output Valid after HCK1 Rising Edge 50 (Note 7) ns
THFS Hold of FS Low after HCK1 Rising Edge 20 ns
TSFS Setup of FS Rising Edge before HCK1 Rising Edge 20 ns
TTTC Delay of TX output TRl-STATE after HCK1 Rising Edge 40 ns
Note r.. This spec is for Ist bit only, Remaining blta are spec'd by transmitter TVTC spec.
Nate 8: Receiver specs TVRS and TVRH are required along with TLFS tor receiver operation using serial decoder.
Serial Decoder Tlmlng Diagram (Modes 3, 4)
FlCltl L_J l_| L:| u-rs-YI-ri-lr
rzrsloil HMS mrslol
" \\\\\\\\\\l\\\\\\\
TVFS -ts1'i-'li--, TLFS cast}
IEFS CASE}
MODE 3 .g h'
TX OUTPUT 1 Nt X other blU I
MODE 4 It nd
TX OUTPUT 1 bit 2 bn cum bit: r
TL/DD/10422- 15
Symbol Parameter Min Max Comments Units
TPFS Number of HCK1 Periods between FS Rising Edges 64 SD Mode 3
TPFS Number of HCK1 Periods between FS Rising Edges 32 SD Mode 4
TAFS Number of HCK1 Falling Edges during FS High 2 62 SD Mode 3
TAFS Number of HCK1 Falling Edges during FS High 2 30 SD Mode 4
TEFS Hold of FS Low after HCK1 Falling Edge 10 Early FS ns
TLFS Setup of FS Rising Edge before HCK1 Falling Edge 45 Late FS, (Note 8) ns
TVFS Delay of TX Output Valid after HCK1 and FS Rising Edges 50 (Note 9) ns
THFS Hold of FS High after HCK1 Falling Edge 20 ns
TSFS Setup of FS Falling Edge before HCK1 Rising Edge 20 ns
TTTC Delay of TX output TRI-STATE after HCK1 Rising Edge 40 ns
Non B: Receiver specs TVRS and TVRH are required along with TLFS for receiver operation using serial decoder.
Note th This spec is for 1st bit only and is measured from the later of either FS or HCK1 rising edge. Remaining bits are spec'd from HCK1 rising edges by
transmitter TVTC spec.
Timing Waveforms (Continued)
Serial Decoder Timing Diagram (Modes 5, 8,7)
HCK1 AS] ''"'"s'1
TEFS «+1 lu', ms TSFS H
ss-ttIll
lllllllllllllllll
TVFC H [t TTTC
OUTPUT
ITT"''"
TLfDD/10422-16
Symbol Parameter Mln Max Comments Units
TPFS Number of HCK1 Periods between FS Rising Edges 34
TAFS Number of HCK1 Falling Edges during FS High 1 32
TEFS Hold of FS Low after HCK1 Falling Edge 10 Early FS ns
TLFS Setup of FS Rising Edge before HCK1 Falling Edge 45 Late FS, (Note 8) ns
TVFC Delay of TX Output Valid after HCK1 Rising Edge 50 (Note 7) ns
THFS Hold of FS High after HCK1 Falling Edge 20 ns
TSFS Setup of FS Falling Edge before HCK1 Rising Edge 20 ns
TTTC Delay of TX output TRI-STATE after HCK1 Rising Edge 40 ns
Note 7: This spec is for 1st bit only. Remaining bits are spec'd by transmitter TVTC spec.
Note 8: Receiver specs TVRS and TVRH am required along with TLFS for receiver operation using serial deoodet.
3OOVQPOdH/EOOVQSOdH/HOOVQ l-OdH
HPC16400E/HPC36400E/HPC46400E
Pin Descriptions
I/O PORTS
Port A is a 16-bit multiplexed address/data bus used for
accessing external program and data memory. Four associ-
ated bus control signals are available on port B. The Ad-
dress Latch Enable (ALE) signal is used to provide timing to
demultiplex the bus. Reading from and writing to external
memory are signalled by W and WA respectively. External
memory can be addressed as either bytes or words with the
decoding controlled by two lines, Bus High Byte enable
(WEE) and Address/Data Line 0 (AG).
Port B is a 16-bit port, with 12 bits of bidirectional IIO. Pins
B10, Bll, B12 and B15 are the control bus signals for the
address/data bus. Port B may also be configured via a func-
tion register BFUN to individually allow each bidirectional
I/O pin to have an alternate function.
BO: TDX UART Data Output
Bl: CFLG1 Closing Flag Output for HDLC #1
Transmitter
B2: CKX UART Clock (Input or Output)
BS: T2I0 Timera l/O Pin
B4: T3l0 Timers I/O Pin
B5: so MlCROWlREfPLt.JS Output
B6: SK MlCROWlRE/PLUS Clock (Input or
Output)
BW. 'ifrD7 Hold Acknowledge Output
B8: TSO Timer Synchronous Output
B9: TSI Timer Synchronous Output
BIO: ALE Address Latch Enable Output for
Address/ Data Bus
B1 1: WA" Address/ Data Bus Write Output
B12: m High Byte Enable Output for Address/
Data Bus; also 8-Blt Mode Strap Input
on Reset.
B13: T82 Timer Synchronous Output
B14: TS3 Timer Synchronous Output
B15: AO Address/Data Bus Read Output
When operating in the extended memory addressing mode,
four bits of port B can be used as follows-
B8: BSO Memory bank switch output 0 (LSB)
" BSI Memory bank switch output 1
B13: BS2 Memory bank switch output 2
B14: BS3 Memory bank switch output 3 (MSB)
Port I is an 8-bit input port that can be read as general
purpose inputs and can also be used for the following func-
tions:
l0: HCK2 HLDC #2 Clock Input
I1: NMI Nonmaskable Interrupt Input
I2: INT2 Maskable Interrupt/ Input Capture
l3: INT3 Maskable lnterrupt/lnput Capture
I4: INT4/HDY Maskable Interrupt/lnput Capture/
Ready Input
I5: SI MlCROWlRE/PLUS Data Input
l6: RDX UART Data Input
l7: HCK1 HDLC #1 Clock and Serial Decoder
Clock Input
Port D is an 8-bit input port that can be read as general
purpose inputs and can also be used for the following func-
tions:
DO; REN1/FS/ Receiver #1 Enable/Serial Decoder
RHCK1 Frame Sync Input/Receiver #1 Clock
DI: TEN1 Transmitter #1 Enable Input
D2: REN2/ Receiver " Enable Input/Receiver
RHCK2 " Clock Input
D3; TEN2 Transmitter " Enable Input
D4: RX1 Receiver fl Data Input
D5: TX1 Transmitter #1 Data Output
D6: RX2 Receiver " Data Input
D7: TX2 Transmitter " Data Output
Note: Any of these pins can be read try software. Therefore, unused lune
tions can be used as general purpose inputs, notabty external enable
lines when the internal aerial decoder is used.
Port R is an 8-bit bidirectional I/O port available for general
purpose l/O operations. Port R has a direction register to
enable each separate pin to be individually defined as an
input or output. It has a data register which contains the
value to be output. In addition, the Port R pins can be read
directly using the Port R pins address.
Pin Descriptions (Continued)
POWER SUPPLIES
Vcc1.Vcca Positive Power Supply (two pins)
GND Ground for On-Chip Logic
DGND Ground for Output Buffers
Note: There are two electrically connected Vcc pins on the chip, GND and
DGND are electrically isolated. Both Vcc pins and both ground pins
must be used
CLOCK PINS
CKI The System Clock Input
CKO The System Clock Output (Inversion of CKI)
Pins CKI and CKO are usually connected across an external
crystal.
CK2 Clock Output (CKI divided by 2)
Connection Diagrams
Pin Grid Array
f INDEX MARK
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TL/DD/10422-17
Top View
See NS Package Number UGBA
Wait States
The HPC16400E provides software selectable Wait States
for access to slower memories and for shared bus applica-
tions. The number of Wait States tor the CPU are selected
by two bits in the PSW register. The number of Wait States
for DMA are selected by a bit in the Message System Con-
figuration register. Additionally, the RDY input may be used
to extend the RD or WR cycle, allowing the HPC to be used
in shared memory applications and allowing the user to in-
terface with slow memories and peripherals.
Power Save Modes
Two power saving modes are available on the HPC16400E:
HALT and IDLE. In the HALT mode, all processor activities
are stopped. In the IDLE mode, the on-board oscillator and
timer T0 are active but all other processor activities are
stopped. In either mode, on-board RAM, registers and IIO
are unaffected (except the HDLC and UART which are re-
OTHER PINS
ih?t5 This is an active low open drain output which
signals an illegal situation has been detected
by the Watch Dog logic.
Bus Cycle Status Output indicates first op-
code fetch.
Bus Cycle Status Output indicates machine
states (skip and interrupt).
Active low input that forces the chip to restart
and sets the ports in a TRI-STATE mode.
Has two uses, selected by a software bit.
This pin is either a READY input to extend
the bus cycle for slower memories or a
HOLD-REQUEST input to put the bus in a
high impedance state for external DMA pur-
poses. In the second case the I4 pin can be-
come the READY input.
RDY/HLD
Plastic and Leaded Chip Carriers
t,s-tuaar,tir,s,t,tetg
8988?:8233’333f333
TUDD/10422-18
Top Vlew
See NS Package Number ELGBA or V68A
HALT MODE
The HPC16400E is placed in the HALT mode under soft-
ware control by setting bits in the PSW. All processor activi.
ties, including the clock and timers, are stopped. In the
HALT mode, power requirements for the HPC16400E are
minimal and the applied voltage (Vcc) may be decreased
without altering the state of the machine. There are two
ways of exiting the HALT mode: via the RE§ET or the NMI.
The KEgtTt input reinitializes the processor. Use of the NMI
input will generate a vectored interrupt and resume opera-
tion from that point with no initialization. The HALT mode
can be enabled or disabled by means of a control register
HALT enable. To prevent accidental use of the HALT mode
the HALT enable register can be modified only once.
IDLE MODE
The HPC16400E is placed in the IDLE mode through the
PSW. In this mode, all processor activity, except the on-
board oscillator and Timer To, is stopped. The HPC16400E
resumes normal operation upon timer TO overflow. As with
the HALT mods, the processor is also returned to full opera-
tion by the RESET or NMI inputs, but without waiting for
oscillator stabilization.
SOOVQVOdHIEOOVQSOdH/EIOOVSl-OdH
HPC16400E/HPC36400E/HPC46400E
HPC16400E Interrupts
Complex interrupt handling is easily accomplished by the
HPC16400E's vectored interrupt scheme. There are eight
possible interrupt sources as shown in Table I.
TABLE L Interrupts
Vector/ Interrupt Source Aptafon
Address Ranking
FFFFIFFFE Reset O
FFFDIFFFC Nonmaskable Ext (NMI) 1
FFFBIFFFA External on I2 2
FFF9IFFF8 External on l3 3
FFF7lFFF6 External on l4 4
FFF5|FFF4 Internal on Timers 5
FFF3|FFF2 Internal on UART 6
FFF1IFFFO End of Message (EOM) 7
The 16400E contains arbitration logic to determine which
interrupt will be serviced first if two or more interrupts occur
simultaneously. Interrupts are serviced after the current in-
struction is completed except for the RESET which is serv-
iced immediately.
The NMI interrupt will immediately stop DMA activity. Byte
transfers in progress will finish thereby allowing an orderly
transition to the interrupt service vector (see DMA descrip-
tion). The HDLC channels continue to operate, and the user
must service data errors that might have occurred during
the NMI service routine.
Interrupt Processing
Interrupts are serviced after the current instruction is com-
pleted except for the RESET, which is serviced immediately.
RESET holds on-chip logic in a reset state while low, and
triggers the RESET interrupt on its rising edge. All other
interrupts are edge-sensitive. NMI is positiveredgo sensitive.
The external interrupts on a I3, and M can be software
selected to be rising or falling edge sensitive.
Interrupt Control Registers
The HPC16400E allows the various interrupt sources and
conditions to be programmed. This is done through the vari-
ous control registers. A brief description of the different con-
trol registers is given below.
INTERRUPT ENABLE REGISTER (ENIR)
RESET and the External Interrupt on I1 am non-maskable
interrupts. The other interrupts can be individually enabled
or disabled. Additionally, a Global Interrupt Enable Bit in the
ENlR Register allows the Maskable interrupts to be collec-
tively enabled or disabled. Thus, in order for a particular
interrupt to request service, both the individual enable bit
and the Global Interrupt bit (GIE) have to be set.
INTERRUPT PENDING REGISTER (IRPD)
The IFtPD register contains a bit allocated for each interrupt
vector. The occurrence of specified interrupt trigger condi-
tions causes the appropriate bit to be set. There is no indi-
cation of the order in which the interrupts have been re-
ceived. The bits are set independently of the fact that the
interrupts may be disabled. IFtPD is a Read/Write register.
The bits corresponding to the external interrupts are normal-
ly cleared by the HPC16400E upon entering the interrupt
servicing routine
For the interrupts from the on-board peripherals, the user
has the responsibility of acknowledging the interrupt
through software.
INTERRUPT CONDITION REGISTER (IRCD)
Three bits of the register select the input polarity of the
external interrupt on I2, I3, and I4.
Servicing the Interrupts
The Interrupt, once acknowledged, pushes the program
counter (PC) onto the stack thus incrementing the stack
pointer (SP) twice, The Global Interrupt Enable (GIE) bit is
reset, thus disabling further interrupts. The program counter
is loaded with the contents of the memory at the vector
address and the processor resumes operation at this point.
At the end of the interrupt service routine, the user does a
RETI instruction to pop the stack, set the GIE bit and return
to the main program. The GIE bit can be set in the interrupt
service routine to nest interrupts if desired. Figure 10 shows
the Interrupt Enable Logic.
The RESET input initializes the processor and sets all pins
at TRI-STATE except CKO, CK2, and WO. HBE and ST2
have pull-downs designed to withstand override. RESET is
an active-low Schmitt trigger input. The processor vectors to
FFFF:FFFE and resumes operation at the address con-
tained at that memory location.
The RESET pin must be asserted low for at least 16 cycles
of the CK2 clock. In applications using the Watchdog tea-
ture, RESET should be asserted for at least 64 cycles of the
CK2 clock.
On application of power, RESET must be held low for at
least five times the power supply rise time to ensure that the
on-chip oscillator circuit has time to stabilize.
Timer Overview
The HPC16400E contains a powerful set of flexible timers
enabling the HP016400E to perform extensive timer func-
tions; not usually associated with microcontrollers.
The HPC16400E contains four 16-bit timers. Three of the
timers have an associated 16-bit register. Timer T0 is a free-
running timer, counting up at a fixed CKI/ 16 (Clock Input/
16) rate. It is used for Watch Dog logic, high speed event
capture, and to exit from the IDLE mode. Consequently, it
cannot be stopped or written to under software control. Tim-
er T0 permits precise measurements by means of the cap-
ture registers l2CR, ISCH, and l4CR. A control bit in the
register TOCON configures timer T1 and its associated reg-
ister R1 as capture registers I3CR and IZCR. The capture
registers IZCR, ISCR. and I4CR respectively, record the val-
ue of timer T0 when specific events occur on the interrupt
pins a a and I4. The control register IRCD programs the
capture registers to trigger on either a rising edge or a falling
edge of its respective input. The specified edge can also be
programmed to generate an interrupt (see Figure IO.
The timers T2 and T3 have selectable clock rates. The
clock input to these two timers may be selected from the
following two sources: an external pin, or derived internally
by dividing the clock input. Timer T2 has additional capabili-
ty of being clocked by the timer T3 underflow. This allows
the user to cascade timers T3 and T2 into a 32-bit timer/
counter. The control register DIVBY programs the clock in-
put to timers T2 and T3 (see Figure 12).
Timer Overview (Continued)
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TL/DDM0422- 19
FIGURE to. Interrupt Enable Logic
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REGISTER
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TL/DD/t0422-21
FIGURE It. Timers T0-T1 Block
TL/DDf10422-20
FIGURE 12. Timers T2-T3 Block
30079t’0dH/ HOOVSSOdH/ 300179l0dH
HPC16400E/HPC36400E/HPC46400E
Timer Overview (Continued)
The timers T1 through T3 in conjunction with their registers
form Timer-Ftegister pairs. The registers hold the pulse du-
ration values. All the Timer-Register pairs can be read from
or written to. Each timer can be started or stopped under
software control. Once enabled, the timers count down, and
upon underflow, the contents of its associated register are
automatically loaded into the timer.
SYNCHRONOUS OUTPUTS
The flexible timer structure of the HPC16400E slmpilfes
pulse generation and measurement. There are four syn-
chronous timer outputs (T SO through T33) that work in con-
junction with the timer T2. The synchronous timer outputs
can be used either as regular outputs or individually pro-
grammed to toggle on timer T2 underflows (see Figure 12).
Maximum output frequency for any timer output can be ob-
tained by setting timer/register pair to zero. This then will
produce an output frequency equal to 'h the frequency of
the source used for clocking the timer.
Timer Registers
There are four control registers that program the timers. The
divide by (DIVBY) register programs the clock input to tim-
ers T2 and T3. The timer mode register (T MMODE) contains
control bits to start and stop timers T1 through T3. It also
contains bits to latch, acknowledge and enable interrupts
from timers T0 through T3.
Timer Applications
The use of Pulse Width Timers for the generation of various
waveforms is easily accomplished by the HPC16400E.
Frequencies can be generated by using the timer/register
pairs. A square wave is generated when the register value is
a constant. The duty cycle can be controlled simply by
changing the register value.
l+'r+-Twl
TLfDDt10422-22
FIGURE 13. Square Wave Frequency Generation
Synchronous outputs based on Timer T2 can be generated
on the 4 outputs TS0-TS3. Each output can be individually
programmed to toggle on T2 underflow. Register R2 con-
tains the time delay between events. Figure " is an exam-
ple of synchronous pulse train generation.
"C-i-tis---;
M: +19]
Fm +114
'l——-1”——]
Te-l F-H-n
TL/DDM0422-23
FIGURE 14. Synchronous Pulse Generation
Watch Dog Logic
The Watch Dog Logic monitors the operations taking place
and signals upon the occurrence of any illegal activity. The
illegal conditions that trigger the Watch Dog logic are poten-
tially infinite loops. Should the Watch Dog register not be
written to before Timer T0 overflows twice, or more often
than once every 4096 counts. an infinite loop condition is
assumed to have occurred. The illegal condition forces the
Watch Out (WO) pin low. The W0 pin is an open drain out-
put and can be connected to the RESET or NMI inputs or to
the users external logic.
MICROWIRE/PLUS
MICROWIRE/PLUS is used for synchronous serial data
communications (see Figure M). MlCROWIRE/PLUS has
an 8-bit parallel-loaded, serial shift register using SI as the
input and so as the output. SK is the clock for the serial
shift register (SIO). The SK clock signal can be provided by
an internal or external source. The internal clock rate is pro-
grammable by the DIVBY register. A DONE flag indicates
when the data shift is completed.
The MICHOWIRE/PLUS capability enables it to interface
with any of National Semitxmdutrtor's MICROWKRE periph-
erals (i.e., ISDN Transceivers, A/D converters, display driv-
ers, EEPROMs).
"IT SIG [ q-------- St
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It CLOCK
A SELECT
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TL/DDMO422-24
FIGURE 15. MlCROWIRE/PLUS
MlCROWlRE/PLUS Operation
The HPC16400E can enter the MICROWIRE/PLUS mode
as the master or a slave. A control bit in the IRCD register
determines whether the HPC16400E is the master or sieve.
The shift clock is generated when the HPC164OOE is config-
ured as a master. An externally generated shift clock on the
SK pin is used when the HPC16400E is configured as a
slave. When the HPC16400E is a master, the DIVBY regis-
ter programs the frequency of the SK clock. The DIVBY
register allows the SK clock frequency to be programmed in
14 selectable steps from 122 Hz to 1 MHz with CKl at
16 MHz.
The contents of the SiO register may be accessed through
any of the memory access instructions. Data waiting to be
transmitted in the $10 register is shifted out on the falling
edge of the SK clock. Serial data on the SI pin is latched in
on the rising edge of the SK clock.
HPC164OOE UART
The HPC16400E contains a software programmable UART.
The UART (see Figure 16) consists of a transmit shift regis-
ter, a receiver shift register and five addressable registers.
as follows: a transmit buffer register (TBUF), a receiver buff-
er register (RBUF), a UART control and status register
(ENU), a UART receive control and status register (ENUR)
and a UART interrupt and clock source register (ENUI). The
ENU register contains flags for transmit and receive func-
tions; this register also determines the length of the data
frame 7 8 or 9 bits) and the value of the ninth bit in trans-
mission. The ENUR register flags framing, parity, and data
overrun errors while the UART is receiving. Other functions
of the ENUR register include saving the ninth bit received in
the data frame, reporting receiving and transmitting status,
and enabling or disabling the UART's Wake-up Mode of op-
eration. The determination of an internal or external clock
saurce is done by the ENUI register, as well as selecting the
number of stop bits (%, l, 1%, 2), selecting between the
synchronous or asynchronous mode and enabling or dis-
abling transmit and receive interrupts.
The clock inputs to the Transmitter and Receiver sections
of the UART can be individually selected to come from ei-
ther an off-chip source on the CKX pin or one of the three
on-chip sources. Presently, two of the on-chip sources. the
Divide-By (DIVBY) Register and the Precision UART Timer
(PUT), are primarily for reasons of upward compatibility from
earlier HPC family members. The most fltntiNt, and accurate
on-chip clocking is provided by the third source: the Baud
Rate Generator (ERG).
The Baud Rate Generator is controlled by the register pair
PSR and BAUD, shown below.
The Prescaier factor is selected by the upper 5 bits of the
PSR register (the PRESCALE field), in units of the CK2
clock from 1 to 16 in y, step increments. The lower 3 bits of
the PSR register, in coniunction with the 8 bits of the baud
register, form the 11-bit BAUDRATE field, which defines a
baud rate divisor ranging from 1 to 2048, in units of the
prescaled clock setected by the PRESCALE field.
In Asynchronous Mode, the resulting baud rate is 1/13 of the
clocking rate selected through the BRG circuit. The maxi-
mum baud rate generated using the BRG is 625 kbaud.
In the Synchronous Mode data is transmitted on the rising
edge and received on the falling edge of the external clock.
Although the data is transmitted and received synchronous-
ly, it is still contained within an asynchronous frame; i.e., a
start bit, parity bit (if selected) and stop bit(s) are still pres-
3-)»zaor'I-4z—
(DC!!!
MTERRUPT
- not CLOCK
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CLOCK _ PUT
SELECT _ mm
-.I PRESCALE meta: F-----) awn mam I
CK2 TL/DD/10422-25
FIGURE 16. UART Block Diagram
_ "ssodi'usm, ----1 F--- aAUD RthSTER -
I‘isizl'ioiwi'lallvlslshisizltlol
'---"gtlu--+----"i""'"o------1
TL/DD/10422-28
UART Baud Rate Generator (BRG) Registers PSR and BAUD
BOOVQVOdHl300V980dH/30079lOdH
HPC16400E/HPC36400E/HPC46400E
UART Attention Mode
The HPC16400E UART features an Attention Mode of oper-
ation. This mode of operation enables the HPC16400E to
be networked with other processors. Typically in such envi-
ronments. the messages consist of addresses and actual
data. Addresses are specified by having the ninth bit in the
data frame set to 1. Data in the message is specified by
having the ninth bit in the data frame reset to 0.
The UART monitors the communication stream looking for
addresses. When the data word with the ninth bit set is
received, the UART signals the HPC16400E with an inter-
rupt. The processor then examines the content of the re-
ceiver buffer to decide whether it has been addressed and
whether to accept subsequent data.
Programmable Serial Decoder
Interface
The programmable serial decoder interface allows the two
HDLC channels to be used with devices employing several
popular Time Division Multiplexing (T DM) serial protocols
for point-to-point and multipoint data exchanges. These pro-
tocols combine the ly and 'D' channels onto common
pins-rtmtalved data, transmit data, clock and Sync, which
normally occurs at an 8 KHz rate and provides framing for
the particular protocol.
The decoder uses the serial link clock and Sync signals to
generate internal enables for the 'D' and 'B' channels,
thereby allowing the HDLC channels to access the appropri-
ate channel data from the multiplexed link.
Additionally, 64 kbit/s to 56 kbits/s rate adaptation can be
done using the Serial Decoder generated enable signals B1
or B2. The rate adaption to 56 kbits/s is accomplished by
using only the first 7 bits of each B channel time slot for
each TDM frame. The transmitter will insert a "I'' in the
eighth bit of each frame. The receiver will only receive the
first seven data bits and skip the eighth bit. See Figure 17
65 kbit/56 kbit Rate Adaption Timing Diagram.
HDLC Channel Description
HDLCIDMA Structure
HDLC 1 HDLC 2
HDLC1 HDLCt HDLC2 HDLC2
Receive Transmit Receive Transmit
DMARI DMATI DMAR2 DMAT2
GENERAL INFORMATION
Both HDLC channels on the HPC16400E are identical and
operate up to 4.65 Mbps. When used in an ISDN Basic Rate
access application, HDLC channel fl has been designated
for use with the 16 kbps D-channel or either B channel and
HDLC #2 can be used with either of the 64 kbps B-chan-
nels. If the 'D' and 'B' channels are present on a common
serial link, the programmable serial decoder interface gen-
erates the necessary enable signals needed to access the
D and B channel data.
There are two sources for the receive and transmit channel
enable signals. They can be internally generated from the
serial decoder interface or they can be externally enabled.
LAPD, the Link Access Protocol for the D channel is derived
from the X.25 packet switching LAPB protocol. LAPD speci-
fies the procedure for a terminal to use the D channel for
the transfer of call control or user-data information. The pro-
cedure is used in both point-to-point and point-to-multipoint
configurations. On the 16400E, the HDLC controller con-
tains user programmable features that allow for the efficient
processing of LAPD Information.
HDLC Channel Pin Description
Each HDLC channel has the following pins associated with
- HDLC Channel Clock Input Signal.
- Receive Serial Data Input. Data latched on
the negative HCK edge.
REN/RHCK-- HDLC Channel Receiver Enable Input/Re-
ceiver Clock Input.
TEN - HDLC Channel Transmitter Enable Input.
TX - Transmit Serial Data Output. Data clocked
out on the positive HCK edge. Data (not in-
cluding CRC) is sent LSB first. TRI-STATE
when transmitter not enabled.
CFLG1 - Closing Flag output for Channel 1.
HDLC Functional Description
TRANSMITTER DESCRIPTION
Data is transferred from external memory through the DMA
controller into the transmit buffer register, from which it is
loaded into a 8-bit serial shift register. The CRC is computed
and appended to the frame prior to the closing flag being
transmitted. Data is output at the TX output pin. If no further
transmit commands are given the transmitter sends out con-
tinous flags, aborts, or the idle pattern as selected by the
control register.
An interrupt is generated when the DMA has transferred the
last byte from RAM to the HDLC channel for a particular
message or on a transmit error condition. An associated
transmit status register will contain the status information
indicating the specific interrupt source.
To support transmitting data packets at an "R" interface for
V.120 in synchronous Ul mode, to support the use of the
HPC in test equipment, or to support proprietary CRC algo-
rithms the transmitter has the option of preventing the trans-
mitting of the hardware generated CRC bytes.
TRANSMITTER FEATURES
lntertrame fill: the transmitter can send either continuous
'I's or repeated flags or aborts between the closing flag of
one packet and the opening flag of the next. When the CPU
commands the transmitter to open a new frame, the inter-
frame fill is terminated immediately.
Abort: the abort sequence. a zero followed by seven ones.
will be immediately sent on command from the CPU or on
an undermn condition in the DMA.
Bit/Byte boundaries: The message length between packet
headers may have any number of bits and is not confined to
an integral number of bytes. Three bits in the control regis-
ter are used to indicate the number of valid bits in the last
byte. These bits are loaded by the users software.
RECEIVER DESCRIPTION
Data is input to the receiver on the RX pin. The receive
clock can be externally input at either the HCK pin or the
REN/RHCK pin.
incoming data is routed through one of several paths de-
pending on whether it is the flag, data, or ORG.
Once the receiver is enabled it waits for the opening flag of
the incoming frame, then starts the zero bit deletion, ad-
HDLC Functional Description (Continued)
310R 32 -l
INSERTED
ONE ,'
_ eltl)Blt2)Bit3)Blt4)Bit5)BltS)Blt7) Y) E
RX A Bit 1) an 2) en 3) Bit , Bit s) an 6) Bit D-e
INSERTED
A ails) Bit 1) 912) am) 8R4) ans) ans) C
Bit " an 1) an 2) an s) an 4) an s) Bit sy-r::: mom
#— on: am
1 NEXT err:
TL/DD/ttHat-at
FIGURE 17. 64 kblt/SG kbit Rate Adaption Timing Diagram
dressing handling and CRC checking. All data between the
Rags is shifted through two 8-bit serial shift registers before
being loaded into the buffer register. The user programma-
ble address register values are compared to the incoming
data while it resides in the shift registers. if an address
match occurs or it operating in the transparent address rec-
ognition mode, the DMA channel is signaled that attention is
required and the data is transferred by it to external memo-
ry. Appropriate interrupts are generated to the CPU on the
reception of a complete frame, or on the occurence of a
frame error.
The receive interrupt, in conjunction with status data in the
control registers allows interrupts to be generated on the
following conditions-trams length error, CRC error, receive
error, abort and receive complete.
To support V.120 Ul data packets at the "R'' interface, pro-
prietary CRC algorithms, and test equipment the two bytes
preceding the closing flag (usually the CRC bytes) will be
loaded into registers. The two bytes can then be read by the
CPU and placed into memory. The DMA address pointers
used for that particular message will already contain the
address that the first byte should be placed into.
RECEIVER FEATURES
Flag sharing: the closing flag of one packet may be shared
as the opening flag of the next. Receiver will also be able to
share a zero between flags-OI 1111101111110 is a valid
two flag sequence for receive (not transmit).
Interframe Ftll: the receiver automatically accepts either re-
peated flags, repeated aborts, or all 'I's as the interframe
Idle: Reception of successive flags as the intertrame fill se-
quence to be signaled to the user by setting the Flag bit in
the Receiver Status register.
Short Frame Rejection: Reception of greater than 2 bytes
but less than 4 bytes between flags will generate a frame
error, terminating reception of the current frame and setting
the Frame Error (FER) status bit in the Receive Control and
Status register. Reception of less than 2 bytes will be ig-
nored.
Abort: the 7 'I's abort sequence will be immediately recog-
nized and will cause the receiver to reinitialize and return to
searching the incoming data for an opening flag. Reception
of the abort will cause the abort status bit in the Interrupt
Error Status register to be set and will signal an End of
Message (EOMR).
Bit/Byte boundaries: The message length between packet
headers may have any number of bits and it is not confined
to an integral number of bytes. Three bits in the status regis-
ter are used to indicate the number of valid bits in the last
Address Recognition: Two user programmable bytes are
available to allow frame address recognition on the two
bytes immediately following the opening flag. When the re-
ceived address matches the programmed value(s), the
frame is passed through to the DMA channel. If no match
occurs, the received frame address information is disregard-
ed and the receiver returns to searching tor the next open-
ing flag and the address recognition process starts anew.
Support is provided to allow recognition of the Broadcast
address. Additionally, a transparent mode of operation is
available where no address decoding is done.
HDLC INTERRUPT CONDITIONS
The end of message interrupt (EOM) indicates that a com-
plete frame has been received or transmitted by the HDLC
controller. Thus, there are four separate sources for this
interrupt, two each from each HDLC channel. The Message
Control Register contains the pending bits for each source.
HDLC ERROR DETECTION
The HDLC/DMA detects several error conditions and re-
ports them in the two Error Status Registers. These condi-
tions are a DMA transmitter underrun, a DMA receiver over-
run, a CRC error, a frame too long, a frame too short, and an
aborted message.
HDLC CHANNEL CLOCK
Each HDLC channel uses the falling edge of the clock to
sample the receive data. Outgoing transmit data is shifted
out on the rising edge of the external clock. The maximum
data rate when using the externally provided clocks is
4.65 Mb/s.
The receiver/transmitter pair can share a single clock input
to save I/O pins, or the inputs can be separated to allow
different receive and transmit clocks. This feature allows the
receiver and transmitter to operate at different frequencies
or enables them to each be synchronized to different parts
of the user's system.
CYCLIC REDUNDACY CHECK
There are two standard CRC codes used in generating the
16-bit Frame Check Sequence (FCS) that is appended to
the end of the data frame. Both codes are supported and
300WVOdH/HOOVQSOdH/BOOVQlOdH
HPC164OOE/HPC36400E/HPC46400E
HDLC Functional
Description (Continued)
the user selects the error checking code to be used through
software control (HDLC control reg). The two error checking
polynomials available are:
(1) CRC-16 (x16 + x15 + x2 + 1)
(2) ccrrr CRC (x16 + x12 + x5 + 1)
SYNCHRONOUS BYPASS MODE
When the BYPAS bit is set in the HDLC control register, all
HDLC framing/formatting functions for the specified HDLC
channel are disabled.
This allows byte-oriented data to be transmitted and re-
ceived synchronously thus "bypassing" the HDLC func.
tions.
LOOP BACK OPERATIONAL MODE
The user has the ability, by setting the appropriate bit in the
register to internally route the transmitter output to the re-
ceiver input, and to internally route the RX pin to the TX pin.
DMA Controller
GENERAL INFORMATION
The HPC16400E uses Direct Memory Access (DMA) logic
to facilitate data transfer between the 2 full Duplex HDLC
channels and external packet RAM. There are four DMA
channels to support the tour individual HDLC channels.
Control of the DMA channels is accomplished through regis-
ters which are configured by the CPU. These control regis-
ters define speciiie operation of each channel and changes
are immediately reflected in DMA operation. In addition to
individual control registers, global control bits (MSS and
MSSC in Message Control Register) are available so that
the HDLC channels may be globally controlled.
The DMA issues a bus request to the CPU when one or
more of the individual HDLC channels request service.
Upon receiving a bus acknowledge from the CPU, the DMA
completes all requests pending and any requests that may
have occurred during DMA operation before returning con-
trol to the CPU. If no further DMA transfers are pending, the
DMA relinquishes the bus and the CPU can again initiate a
bus cycle.
Four memory expansion bits have been added for each of
the four channels to support data transfers into the expand-
ed memory bank areas.
The DMA has priority logic for servicing DMA requests. The
priorities are
Ist priority ................... Receiver Channel 1
2nd priority ................... Transmit channel 1
3rd priority .................... Receive channel 2
4th priority ................... Transmit channel 2
RECEIVER DMA OPERATION
The receiver DMA consists of a shift register and two buff-
ers. A receiver DMA operation is initiated by the buffer regis-
ters. Once a byte has been placed in a buffer register from
the HDLC, it generates a request and upon obtaining control
of the bus, the DMA places the byte in external memory.
RECEIVER REGISTERS
All the following registers are Read/Write
A. Frame Length Register
This user programmable 16-bit register contains the max-
imum number of bytes to be placed in a data "block". If
this number is exceeded. a Frame Too Long error is gener-
ated. DMA is stopped to prevent memory from being over-
written, however the receiver continues until the closing tlag
is received in order to check the DRC.
B.CNTRLADDRI For split frame operation, the
DATA ADDR 1 CNTRL ADDR register contains the
external memory address where
CNTRLADDR2 the Frame Header (Control & Ad-
DATA ADDR 2
dress fields) are to be stored and
the DATA ADDR register contains
an equivalent address for the Inter-
mation field.
For non-split frame operation, the
CNTRL and DATA ADDR registers
each contain the external memory
address for entire frames.
TRANSMITTER DMA OPERATION
The transmitter DMA consists of a shift register and two
butters. A transmitter DMA cycle is initiated by the TX data
buffers. The TX data buffers generate a request when either
one is empty and the DMA responds by placing a byte in the
butter. The HDLC transmitter can then accept the byte to
send when needed, upon which the DMA will issue another
request, resulting in a subsequent DMA cycle.
TRANSMITTER REGISTERS
The following registers are Read/Write:
FIELD ADDRESS1 Field Address 1 and Field Address
BYTE COUNT1 2 are starting addresses of blocks
FIELD ADDRESS 2 of information to be transmitted.
Byte Count 1 and Byte Count 2 are
BYTE COUNT 2 the number of bytes in the block to
be transmitted.
Shared Memory Support
Shared memory access provides a rapid technique to ex-
change data. it is effective when data is moved from a pe-
ripheral to memory or when data is moved between blocks
of memory. A related area where shared memory access
proves effective is in multiprocessing applications where
two CPUs share a common memory block. The HPG16400E
supports shared memory access with two pins. The pins are
the RDY/m input pin and the FrLWA output pin. The user
can software select either the Hold or Ready function on the
RDY/FIE pin by the state of a control bit. The HLDA output
must be selected as the HLDA output on pin B7 by soft-
The host uses DMA to interface with the HPC16400E. The
host initiates a data transfer by activating the m input of
the HPC16400E. in response, the HPC16400E places its
system bus in a TRI-STATE Mode, freeing it for use by the
host. The host waits for the acknowledge signal (HLDA)
from the HPC164OOE indicating that the sytem bus is free.
On receiving the acknowledge, the host can rapidly transfer
data into, or out of, the shared memory by using a conven-
tional DMA controller. Upon completion of the message
transfer, the host removes the HOLD request and the
HPC16400E resumes normal operations. See Figure M
(HPC16400E shared Memory Using HOLD).
An alternate approach is to use the Ready function avail-
able on either the RDY/m) pin or the INT4/RDY pin. See
Figure 19 (HPC16400E Shared Memory Using READY).
This technique is often required when the HPC is sharing
memory over a system backplane bus.
Shared Memory Support (Continued)
PROCESSOR
HPCI Moor
(rN7rt,cs) HLDA
, ARBITRATION ----
3 's "
I6 W_R
t EN y
Rot tt H Lt)
LOCAL SHARED LOCAL
MEMORY MEMORY umomr
FIGURE 18. HPC16400E Shared Memory Uslng HOLD
PROCESSOR
HPCI 6400!
(rT6, W, cs) (rro, w‘n. CS)
_--I ARBITRA‘HON 1
3 " 'N 1 l / " 3
RT) Rt L
" EN DI =
ROY tt h ROY
LOCAL SHARED LOCAL
MEMORY MEMORY MEMORY
FIGURE 19. HPC16400E Shared Memory Uslng READY
TL/DD/10422-27
TL/ DD/10422-28
EOOVQVOdH/3007980dH/30079l-OdH
HPC16400E/HPC36400E/HPC46400E
Memory
The HPC164OOE has been designed to offer flexibility in
memory usage. A total address space of 64 kbytes can be
addressed with 256 bytes of RAM available on the chip it-
Program memory addressing is accomplished by the 16-bit
program counter on a byte basis. Memory can be addressed
directly by instructions or indirectly through the B, X and SP
registers. Memory can be addressed as words or bytes.
Words are always accessed on even-byte boundaries. The
HP016400E uses memory-mapped organization to support
registers, l/O and on-ehip peripheral functions.
The HPC16400E memory address space extends to 64
kbytes and registers and I/O are mapped as shown in Table
Extended Memory Addressing
If more than 64k of addressing is desired in a HPC164OOE
system, on board bank select circuitry is available that al-
lows four I/O lines of Port B (Be, B9, B13, Bl4) to be used
in extending the address range. This gives the user a main
routine area of 32k and 16 banks of 32k each for subroutine
and data, thus getting a total of 536.5k of memory.
Note: it all four lines are not needed for memory expansion, the unused
lines can be used as general purpose inputs.
The Extended Memory Addressing mode is entered by set-
ting the EMA control bit in the Message Control Register. If
this bit is not set, the port B lines (B8, B9, B13, B14) are
available as general purpose IIO or synchronous outputs as
selected by the BFUN register.
The main memory area contains the interrupt vectors &
service routines, stack memory, and common memory for
the bank subroutines to use. The 16 banks of memory can
contain program or data memory (note: since the on chip
resources are mapped into addresses 0000-01FF, the first
512 bytes of each bank are not usable, actual available
memory is 536.5k).
TABLE II. Memory Map
FFFF-FFFO lntetrupt Vectors
FFEF-FFDO JSRP Vectors
FFCF-FFCE
' : External Expansion USER MEMORY
0201 -0200
01 FF-tMFE
.. '. On Chip RAM USER RAM
01C1 -01CO
01 ac CRC Byte 2
01BA cnc Byte 1
01 B8 Error Status
01 B6 Receiver Status
0184 Cntrl HDLC ' 2
0182 Recr Addr Comp Reg 2
01 BO Ftecr Addr Comp Reg 1
tMAC CRC Byte 2
01AA cnc Byte 1
01A8 Error Status
01A6 Receiver Status
01M Cntrl HDLC ' 1
01A2 Flecr Addr Comp Reg 2
01 A0 Recr Addr Camp Reg 1
0195-0194 Watch Dog Register Watch Dog Logic
0193-0192 TOCON Register
0191-0190 TMMODE Register
01BF-01BE DIVBY Register
tMttD-018C T3 Timer
018B-018A R3 Register .
0189-0188 T2 Timer Timer Block T0-T3
0187-0186 R2 Register
0185-0184 1208 Register/ R1
0183-0182 ISCFI Ragister/ T1
0t81-0180 14CR Register
017F-017E Baud Counter .
0170-0170 Baud Register UART Timer
0t79-0178 Byte Count 2
0177-0176 Field Addr 2
0t75-0174 Byte Count 1 DMAT ' 2 (Xmit)
OT73-0172 Field Addr 1
01 71 -0170 Xmit Cntrl & Status
0163-016A Frame Length
0169-0168 Data Addr2
0167-0166 Cntrl Addr 2
0165-0164 Data Addr1 DMAR ' 2 (Remo
0163-0162 Cntrt Addr 1
0161 -0160 Retw Cntrl 6 Status
Nola: All unused addresses axe reserved by National Semiconductor
0159-0158 . Bytes 2
0157-0156 Field Addr 2
0155-0154 f Bytes1 DMAT f 1 (Xmit)
0153-0152 Field Addr 1
0151 -0150 Xmit Cntrl a Status
014B-014A Frame Length
0149-0148 Data Addr 2
0147-0146 Cntrl Addr 2 DMAR . 1 (Recv)
0145-0144 Data Addr1
0143-0142 Cntrl Addr 1
0141-0140 Recv Cntrl & Status
0120 Baud
012A PSR . Prescaler
0128 ENUR Register
0126 TBUF Register
0124 RBUF Register UART
0122 ENUI Register
0120 ENU Register
010E Port R Pins
0100 DIR R Register
010A Port R Data Register
0108 Message System Configuration
0106 Serial Decoder/ Enable PORTS R & D
Configuration Reg
0104 Message Pending
0102 Message System Control
0100 Port D Input
00F5-00F4 BFUN Register
00F3-00F2 DIR B Register PORT B
GOES Chip Revision Register
00E3 -00E2 Port B
OODD-OODG Halt Enable Register PORT CONTROL
ODDS Port I Input Register & INTERRUPT
00D6 SIO Register CONTROL
00D4 IRCD Register REGISTERS
OOD2 IRPD Register
00D0 ENIR Register
OOCF-DOCE X Register
ooCD-00CC B Register
ODCB-OOCA K Register
0009-0008 A Register HPC CORE
00C7-00C6 PC Register R EGISTERS
t)0C5-00C4 SP Register
0003-0002 (Reserved)
0000 PSW Register
t7oBF-00BE On Chip
: : RAM USER RAM
0001 -0000
Design Considerations
Designs using the HPC family of 16-bit high speed CMOS
microcontrollers need to follow some general guidelines on
usage and board layout.
Floating inputs are a frequently overlooked problem. CMOS
inputs have extremely high impedance and, if left open, can
Mat to any voltage possibly causing internal devices to go
into active mode and draw DC current. You should thus tie
unused inputs to Vcc or ground, either through a resistor or
directly. Unlike the inputs, unused outputs should be left
floating to allow the output to switch without drawing any DC
current.
To reduce voltage transients, keep the supply line's parasit-
ic inductances as low as possible by reducing trace lengths,
using wide traces, ground planes, and by decoupling the
supply with bypass capacitors. in order to prevent additional
voltage spiking, this local bypass capacitor must exhibit low
inductive reactance. You should therefore use high frequen-
cy ceramic capacitors and place them very near the IC to
minimize wiring inductance.
. Keep Vcc bus routing short. When using double sided or
multilayer circuit boards, use ground plane techniques.
q Keep ground lines short, and on PC boards make them
as wide as possible, even if trace width varies. Use sepa-
rate ground traces to supply high current devices such as
relay and transmission line drivers.
. In systems mixing linear and logic functions and where
supply noise is critical to the analog components' per-
formance, provide separate supply buses or even sepa-
rate supplies.
0 When using local regulators, bypass their inputs with a
tantalum capacitor of at least 1 pi: and bypass their out-
puts with a 10 " to 50 p.F tantalum or aluminum electro-
lytic capacitor.
q If the system uses a centralized regulated power supply,
use a " p.F to 20 “F tantalum electrolytic capacitor or a
50 p.F to 100 pF aluminum electrolytic capacitor to de-
couple the Vcc bus connected to the circuit board.
0 Provide iocaiized decoupling. For random logic, a rule
of thumb dictates approximately 10 nF (spaced
within 12 cm) per every two to five packages, and 100 nF
for every 10 packages. You can group these capacitanc-
es. but it's more effective to distribute them among the
ICs. lf the design has a fair amount of synchronous logic
with outputs that tend to switch simultaneously, addition.
al decoupling might be advisable. Octal flip-flop and buff-
ers in bus-oriented circuits might also require more de-
coupling. Note that wire-wrapped circuits can require
more decoupling than ground plane or multilayer PC
boards.
Rec tiK0
XTAL 200k HP016400E
C2 T T C1
TL/DDM0422-20
A recommended crystal oscillator circuit to be used with the
HPC is shown below. See table for recommended compo-
nent values. The recommended values given in the table
below have yielded consistent results and are made to
match a crystal with a 20 pF load capacitance, with some
small allowance for layout capacitance.
A recommended layout for the oscillator network should be
as close to the processor as physically possible, entirely
within 1" distance. This is to reduce lead inductance from
long PC traces, as well as interference from other compo-
nents, and reduce trace capacitance. The layout should
contain a large ground plane either on the top or bottom
surface of the board to provide signal shielding, and a con-
venient location to ground both the HPC, and the case of
the crystal.
It is very critical to have an extremely clean power supply for
the HPC crystal oscillator. Ideally one would like a Vcc and
ground plane that provide iow inductance power iines to the
chip. The power planes in the PC board should be decou-
pled with three decoupling capacitors as close to the chip
as possible. A 1.0 “F, a 0.1 pF, and a 0.001 " dipped mica
or ceramic cap mounted as close to the HPC as is physically
possible on the board, using the shortest leads, or surface
mount components. This should provide a stable power
supply, and noiseless ground plane which will vastly im-
prove the performance of the crystal oscillator network.
HPC Oscillator Table
Ic (MHz) Roe tn) ttt (pr) C2 (pF)
2 50 82 1 00
4 50 62 75
6 50 50 56
8 50 47 50
10 50 39 50
12 o 39 39
1 4 0 33 39
16 0 33 39
1 8 0 33 33
20 0 33 33
Crystal Specifications:
"AT" cut, parallel resonant crystals tuned
to the desired irequency with the ioiiowing
specifications are recommended:
Series Resistance < 650
Loading Capacitance: CL '= 20 pF
3007973dHlElOOVQSOdH/EOOVSlOdH
HPC164OOE/ HPC36400E/ HPC46400E
HPC16400E CPU
The HPC16400E CPU has a 16-bit ALU and six 16-bit regis-
Arithmetic Logic Unit (ALU)
The ALU is 16 bits wide and can do 16-bit add, subtract and
shift or logic AND, OR and exclusive OR in one timing cycle.
The ALU can also output the carry bit to a 1-bit C register.
Accumulator (Al Register
The 16-bit A register is the source and destination register
for most VO, arithmetic, logic and data memory access op-
erations.
Address (B and X) Registers
The 16-btt B and X registers can be used for indirect ad-
dressing. They can automatically count up or down to se-
quence through data memory.
Boundary (K) Register
The 16-bit K register is used to set limits in repetitive loops
of code as register B sequences through data memory.
Stack Pointer (SP) Register
The 16-bit SP register is the stack pointer that addresses
the stack. The SP register is incremented by two for each
push or cail and decremented by two for each pop or return.
The stack can be placed anywhere in user memory and be
as deep as the available memory permits.
Program (PC) Register
The 16-bit PC register addresses program memory.
Addressing Modes
ADDRESSING MODES--ACCUMULATWt AS
DESTINATION
Register Indirect
This is the "normal" mode of addressing for the
HP016400E (instructions are single-byte). The operand is
the memory addressed by the B register tor X register for
some instructions).
Direct
The instruction contains an 8-bit or 16-bit address field that
directly points to the memory for the operand.
indirect
The instruction contains an 8-bit address field. The contents
of the WORD addressed points to the memory for the oper-
Indexed
The instruction contains an 8-bit address field and an tr. or
16-bit displacement field. The contents of the WORD ad-
dressed is added to the displacement to get the address of
the operand.
Immediate
The instruction contains an 8-bit or 16-bit immediate field
that is used as the operand.
Register indirect (Auto increment and Document)
The operand is the memory addressed by the X register.
This mode automatically increments or decrements the X
register (by 1 for bytes and by 2 for words).
Register indirect (Auto Increment and Decrement) with
Conditional Skip
The operand is the memory addressed by the B register.
This mode automatically increments or decrements the B
register (by 1 for bytes and by 2 for words). The B register is
then compared with the K register. A skip condition is gener-
ated it B goes past K.
ADDRESSING MODES-DIRECT MEMORY AS
DESTINATION
Direct Memory to Direct Memory
The instruction contains two 8- or 16-bit address fields. One
field directly points to the source operand and the other fiteld
directly points to the destination operand.
Immediate to Direct Memory
The instruction contains an 8- or 16-bit address field and an
8. or 16-bit immediate field. The immediate field is the oper-
and and the direct field is the destination.
Double Register Indirect using the B and X Registers
Used only with Reset, Set and IF bit instructions; a specific
bit within the 64 kbyte address range is addressed using the
B and X registers. The address of a byte of memory is
formed by adding the contents of the B register to the most
significant 13 bits of the X register. Tho specific bit to be
modified or tested within the byte of memory is selected
using the least significant 3 bits of register X.
2..1 50
HPC Instruction Set Description
Mnemonlc I Deaerlptlon
ARITHMETIC INSTRUCTIONS
Action
ADD Add MA+ Meml - MA carry - C
ADDS Add short imm8 MA + imme - MA carry - 0
ADC Add with carry MA + Merni+ C -> MA carry - C
DADC Decimal add with carry MA + Meml + C - MA (Decimal) carry - C
SUBC Subtract with carry MA- Meml + C - MA carry - C
DSUBC Decimal subtract w/carry MA-- Meml + C .-r MA (Daclmal) carry - C
MULT Multiply (unsigned) MA'MemI - MA 8 X, 0 - K, 0 - C
DIV Divide (unsigned) MA/Meml - MA, rem. - X, 0 - K, 0 - C
DIVD Divide Double Word (unsigned) (x8 MA)/Meml - MA, rem - X, 0 --- K carry - C
lFEQ If equal Compare MA & Meml, Do next if equal
IFGT If greater than Compare MA & Meml, Do next if MA - Meml
AND Logical and MA and Meml - MA
OR Logical or MA or Meml -+ MA
XOR Logical exclusive-or MA xor Meml - MA
MEMORY MODIFY INSTRUCTIONS
INC Increment Mam + 1 - Mem
DECSZ Decrement, skip ifO Mem -I - Mam. Skip next if Mam = 0
BIT INSTRUCTIONS
SBIT Set bit 1 - Mem.bit (bit is 0 to 7 immediate)
RBIT Reset bit 0 - Mem.bit
IFBIT If bit If Mem.bit is true, do next instr.
MEMORY TRANSFER INSTRUCTIONS
LD Load Meml - MA
Load, incrldecr X Mem(X) - A, X tl (or 2) - X
ST Store to Memory MA - Mam
X Exchange A - Mem; Mem 4-» Mam
Exchange, incrldecr X A -.-. Mem(X). X Al (or 2) - X
PUSH Push Memory to Stack W .-- W(SP), SP+ 2 -+ SP
POP Pop Stack to Memory SP -2 --r SP, W(SP) - w
LDS Load A, incr/decr B, Mem(B) - A, B tl (or 2) - B,
Skip on condition Skip next if B greater/lass than K
XS Exchange, incr/decr B, Mem(B) <--> AB kl (or 2) - B,
Skip on condition Skip next if B greater/Iess than K
REGISTER LOAD IMMEDIATE INSTRUCTIONS
LD A Load A immediate imm -+ A
LD B Load B immediate imm - B
LD K Load K immediate imm - K
LD X Load X immediate imm .-- X
LD BK Load B and K immediate imm .-- B,imm -+ K
ACCUMULATOR AND 0 INSTRUCTIONS
CLFI A Clear A
INC A Increment A
DEC A Decrement A
COMP A Complement A
SWAP A Swap nibbles of A
RRC A Rotate A right thru C
RLC A Rotate A left thru C
SHR A Shift A right
SHL A Shift A left
SC Set C
RC Reset C
IFC IF C
IFNC IF not C
A +I-+A
A --1-rA
I's compltsrmmtofA-tA
A15:12 - A11:8 - A7:4 - A3:0
C-rA15 - ... -rA0--ro
C<-A15 e-- ... q--A0<--C
0--rA15-r...-rA0-rC
ce-AIO- ... -Ao--o
DonextifC=1
Donex1i10=0
EOOVSPOdHIEOOVQGOdH/EOOPQlOdH
HPC16400ElHPCSS4OOE/HPC464OOE
HPC Instruction Set Description (Continued)
"tttttttttttttt I Description
TRANSFER OF CONTROL INSTRUCTIONS
Action
JSRP Jump subroutine from table
JSR Jump subroutine relative
JSRL Jump subroutine long
JP Jump relative short
JMP Jump relative
JMPL Jump relative long
JlD Jump indirect at PC + A
NOP No Operation
RET Return
RETS Return then skip next
RETI Return from interrupt
PC - W(SP),SP+2 _ SP
W(table#) - PC
PC _ W(SP),SP+2 - SP,PC+ ' --> PC
(#is + 1024 to -1023)
PC - W(SP).SP+2 - SP,PC+ * - PC
PC+ ' - PC(# is +32 to -31)
PC+ ' - PC(#is + 256 to -255)
PC+ ' - PC
PC+A+1 - PC
then Mem(PC)+ PC - PC
PC - PC + 1
SP-2 - SP.W(SP) - PC
SP-? - SP,W(SP) - PC, & skip
SP--? - SP,W(SP) --> PC, interrupt re-enabled
Note: W is 16-bit word of memory
MA is Accumulator A or direct memory (8 or 16-bit)
Mam is 8-bit byte or 165-bit word at memory
Mernl is 8- or 16-bit memory or 8 or ttr-bit immedate data
imm is 8-bit or 16-bit immediate data
Memory Usage
For information on memory usage and instruction timing
please refer to the HPC16400E User's Manual (see page 25
for ordering information).
Code Efficiency
The HPC16400E has been designed to be extremely code-
efficient. The HPC16400E looks very good in all the stan-
dard coding benchmarks; however. it is not realistic to rely
only on benchmarks. Many large jobs have been pro-
grammed onto the HPC16400E, and the code savings over
other popular microcontrollers has been considerable.
Reasons for this saving of code include the following:
SINGLE BYTE INSTRUCTIONS
The majority of instructions on the HPG16400E are single-
byte. There are two especially code-saving instructions:
JP is a 1-byte jump. True, it can only jump within a range of
plus or minus 32, but many loops and decisions are often
within a small range of program memory. Most other micros
need 2-byte instructions tor any short jumps.
JSRP is a 1-byte call subroutine. The user makes a table of
his 16 most frequently called subroutines and these calls
will only take one byte. Most other micros require two and
even three bytes to call a subroutine. The user does not
have to decide which subroutine addresses to put into his
table; the assembler can give him this information.
EFFICIENT SUBROUTINE CALLS
The 24ryte JSR instructions can call any subroutine within
plus or minus 1k of program memory.
MULTIFUNCTION iNSTRUCTlONS FOR DATA MOVE-
MENT AND PROGRAM LOOPING
The HP016400E has single-byte instructions that perform
multiple tasks. For example, the XS instruction will do the
following:
1. Exchange A and memory pointed to by the B register
2. increment or decrement the B register
3. Compare the B register to the K register
4. Generate a conditional skip if B has passed K
The value of this multipurpose instruction becomes evident
when looping through sequential areas of memory and exit-
ing when the loop is finished.
BIT MANIPULATION INSTRUCTIONS
Any bit of memory, I/O or registers can be set. reset or
tested by the single byte bit instructions. The bits can be
addressed directly or indirectly. Since all registers and I/O
are mapped into the memory. it is very easy to manipulate
specific bits to do efficient control.
DECIMAL ADD AND SUBTRACT
This instruction is needed to interface with the decimal user
world.
It can handle both 16-bit words and tMrit bytes.
The 16-bit capability saves code since many variables can
be stored as one piece of data and the programmer does
not have to break his data into two bytes. Many applications
store most data in 4-digit variables. The HPC16400E sup-
plies 8-bit byte capability for 2-digit variables and literal vari-
ables.
MULTIPLY AND DIVIDE INSTRUCTIONS
The HPC16400E has 16-bit multiply, 16-bit by 16-bit divide,
and 32-bit by 16-bit divide instructions. This saves both
code and time. Multiply and divide can use immediate data
or data from memory. The ability to multiply and divide by
immediate data saves code since this function is often
needed for sealing, base conversion, computing indexes of
arrays, etc.
Part Selection
The HPC family includes devices with many different op-
tions and configurations to meet various application needs.
The number HPC16400E has been generally used through-
out this datasheet to represent the whole family of parts,
The following chart explains how to order various options
available when ordering HPC family members.
Note: All options may not currently be available.
HPCt6400E V 20
Speed In MHz
Package Type
U = Pin Grid Array (PGA)
V = Plastic Chip Carrier
(PLCC)
L = Leaded Ceramic Chip
Carrier (LDCC)
T = Tape Pak (T P)
Temperature
4 = Commercial (0''C TO
+ 70°C)
a = Industrialt-4ty'C to
+ 85°C)
1 = Military (-55''C to
+ 125'C)
FIGURE 15. HPC Family Part Numbering Scheme
EXAMPLES
HPC46400EV20-commemial temp (ty' to +70''C), PLCC
HPC36400EV20-lndustrial temp (- 4ty'C to + 85°C), PLCC
Development Support
HPC DEVELOPMENT SYSTEM
The HPC Development System is an in-system emulator
(ISE) designed to support National Semiconductor's entire
family of HPC microcontrollers. The compiete package of
hardware and sottware tools, when combined with an IBM
or compatible PC, provides a powerful tool for the develop-
ment of High Performance mierocontroller based products.
The stand alone unit comes complete with vertically mount-
ed circuit boards, a power supply, and an external emulation
pod. It is packaged in a UL approved, fan cooled steel case.
The unit can be connected to a PC host via an RS-232 link.
The software package includes a C compiler, linker, cross
assembler, librarian, operating manuals and a source level
debugger program.
The ISE provides fully transparent in-eireuit emulation at
speeds up to 20 MHz 1 waitstate. A 2K word (48-bit wide)
real-time trace assists in the non-instrusive monitoring of
the system. EPROM programming can be done through the
use of the extemeily mounted EPROM socket. On-Iine help
functions and a diagnostics option allow the user to reduce
his programming and debugging time. 8 hardware break-
points (address/range located), 64 kbytes of user memory.
and 8 external trace lines are some of the other features
designed into the kit.
Development Tools Selectlon Table
Microcontroller Part Number Description Includes
HPC-DEV-ISE2 HPC In-System Emulator HPC Micrtxxmtroller Development
with PLCC Pod Cable System Manual
HPC16400E/HPC46400E User's Manual
HPC-DEV-tBMC C-Compiler for IBM PC C-Compiler Manual
HPC1 6 400E and Compatibles Assembler Manual
HPC-DEV-IBMA Helocatable Assembler Software Assembler Manual
for IBM PC and Compatibles
HPC-DEV-WDBC C Source/Symbolic Debugger Debugger User's Manual
with MS-Windows
Support Doeuments
Description Order Number
HPC16400E User's Manual 420420213-001
300t970dHIEOOVQEOdH/EOOVBl-OdH
HPC16400E/HPC36400E/HPC46400E
Development Support (Continued)
DIAL-A-HELPER
Dial-A-Helper is a service provided by the Microcontroller
Applications Group. Dial-A-Helper is an electronic bulletin
board information system and additionally, provides the ca-
pability of remotely accessing the development system at a
customer site.
INFORMATION SYSTEM
The Dial-A-Helper system provides access to an automated
information storage and retrieval system that may be ac-
cessed over standard diai-up telephone lines 24 hours a
day. The system capabilities include a MESSAGE SECTION
(electronic mail) for communications to and from the Micro-
controller Applications Group and a FILE SECTION which
consists of several file areas where valuable application
software and utilities can be found. The minimum require-
ment for accessing Dial-A-Helper is a Hayes compatible mo-
If the user has a PC with a communications package then
files from the FILE SECTION can be down loaded to disk for
later use.
Order PIN: MOLE-DlAL-A-HLP
information System Package Contains:
Dial-A-Helper Users Manual
Public Domain Communications Software
FACTORY APPLICATIONS SUPPORT
DiaI-A-Helper also provides immediate factory applications
support. If a user is having difficulty in operating a develop-
ment system, he can leave messages on our electronic bul-
Ietin board, which we will respond to.
(408) 721 -5582
300 or 1200 baud
Voice:
Modem: (408) 739-1162
Set-Up:
Length: 8-Bit
Parity: None
Stop Bit: 1
Operation: 24 Hrs, 7 Days
This datasheet has been :
www.ic-phoenix.com
Datasheets for electronic components.
National Semiconductor was acquired by Texas Instruments.
corp/docs/irwestor_relations/Pr_09_23_201 1_national_semiconductor.html
This file is the datasheet for the following electronic components:
HPC36400EV20 - product/hpc36400ev20?HQS=TI-nulI-nuIl-dscataIog-df-pf-null-wwe
HPC364OOET20 - product/hpc36400et20?HQS=T|-nu|I-nulI-dscatalog-df—pf—nuII-wwe
HPC36400EU20 - product/hpc36400eu20?HQS=T|—nuIl-nulI-dscatalog-df—pf—null-wwe
HPC36400EL20 - product/hpc36400el20?HQS=T|—nu|I-nuIl—dscatalog-df-pf-nulI-wwe
HPC464OOEL20 - product/hpc46400e|20?HQS=TI-nu|I-nuIl-dscatalog-df-pf-nulI-wwe
HPC464OOET20 - product/hpc46400et20?HQS=T|-nu|I-nulI-dscatalog-df—pf—nuII-wwe
HPC46400EU20 - product/hpc46400eu20?HQS=T|—nuIl-nulI-dscatalog-df—pf—null-wwe
HPC46400EV20 - product/hpc46400ev20?HQS=T|—nulI-nuIl-dscataIog-df-pf-null-wwe
HPC16400EV20 - product/hpc16400ev20?HQS=TI-nulI-nuIl-dscataIog-df-pf-null-wwe
HPC16400EU20 - product/hpc16400eu20?HQS=T|—nuIl-nulI-dscatalog-df—pf—null-wwe
HPC16400ET20 - product/hpc16400et20?HQS=T|-nu|I-null-dscatalog-df—pf—nuII-wwe
HPC16400EL20 - product/hpc16400el20?HQS=TI-nuIl-nu|I—dscatalog-df-pf-nuII-wwe

Partno	Mfg	Dc	Qty	Available	Descript
HPC36400EV20	NS	N/a	16	avai	20 MHz, 100 mA, 7 V, high-performance communication microcontroller
HPC46400EV20	NS	N/a	15	avai	20 MHz, 100 mA, 7 V, high-performance communication microcontroller
HPC46400EV20	NSC	N/a	285	avai	20 MHz, 100 mA, 7 V, high-performance communication microcontroller