HEF4894BT ,12-stage shift-and-store register LED driver HEF4894B12-stage shift-and-store register LED driverRev. 8 — 22 November 2011 Product data sheet1.
HEF4894BT ,12-stage shift-and-store register LED driverLogic diagram5. Pinning information5.1 Pinning STR 1 20 VDDDO 2 19ECP 3 18 QP6QP0 4 17 QP75 16QP1 Q ..
HEF4894BT ,12-stage shift-and-store register LED driverFeatures and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized ..
HEF4894BT ,12-stage shift-and-store register LED driverGeneral descriptionThe HEF4894B is a 12-stage serial shift register. It has a storage latch associa ..
HEF4894BT ,12-stage shift-and-store register LED driverFeatures and benefits Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized ..
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HEF4894BT
12-stage shift-and-store register LED driver
1. General descriptionThe HEF4894B is a 12-stage serial shift register. It has a storage latch associated with
each stage for strobing data from the serial input (D) to the parallel LED driver outputs
(QP0 to QP11). Data is shifted on positive-going clock (CP) transitions. The data in each
shift register stage is transferred to the storage register when the strobe (STR) input is
HIGH. Data in the storage register appears at the output whenever the output enable (OE)
input signal is HIGH.
Two serial outputs (QS1 and QS2) are available for cascading a number of HEF4894B
devices. Serial data is available at QS1 on positive-going clock edges to allow high-speed
operation in cascaded systems with a fast clock rise time. The same serial data is
available at QS2 on the next negative going clock edge. This is used for cascading
HEF4894B devices when the clock has a slow rise time.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefits Fully static operation5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C and 40 C to +125C Complies with JEDEC standard JESD 13-B
3. Ordering information
HEF4894B
12-stage shift-and-store register LED driver
Rev. 8 — 22 November 2011 Product data sheet
Table 1. Ordering informationAll types operate from 40 C to +125 C.
HEF4894BP DIP20 plastic dual in-line package; 20 leads (300 mil) SOT146-1
HEF4894BT SO20 plastic small outline package; 20 leads; body width 7.5 mm SOT163-1
HEF4894BTT TSSOP20 plastic thin shrink small outline package; 20 leads; body width 4.4 mm SOT360-1
NXP Semiconductors HEF4894B
12-stage shift-and-store register LED driver
4. Functional diagramNXP Semiconductors HEF4894B
12-stage shift-and-store register LED driver
5. Pinning information
5.1 PinningNXP Semiconductors HEF4894B
12-stage shift-and-store register LED driver
5.2 Pin description
6. Functional description[1] H= HIGH voltage level; L= LOW voltage level; X = don’t care; = LOW-to-HIGH clock transition; = HIGH-to-LOW clock transition; = high-impedance OFF-state.
[2] Q10S = the data in register stage 10 before the LOW to HIGH clock transition.
[3] Q11S = the data in register stage 11 before the HIGH to LOW clock transition.
Table 2. Pin description 2 serial input
QP0 to QP11 4, 5, 6, 7, 8, 9, 18, 17, 16, 15, 14, 13 parallel output
QS1 11 serial output
QS2 12 serial output 3 clock input
STR 1 strobe input 19 output enable input
VDD 20 supply voltage
VSS 10 ground (0V)
Table 3. Function table[1]At the positive clock edge the information in the 10th register stage is transferred to the 11th register stage and the QS output L X X Z Z Q10S no change L X X Z Z no change Q11S H L X no change no change Q10S no change HH L Z QPn 1 Q10S no change HH HL QPn1 Q10S no change H H H no change no change no change Q11S
NXP Semiconductors HEF4894B
12-stage shift-and-store register LED driver
7. Limiting values[1] For DIP20 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO20 package: Ptot derates linearly with 8 mW/K above 70 C.
[3] For TSSOP20 package: Ptot derates linearly with 5.5 mW/K above 60 C.
Table 4. Limiting valuesIn accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage 0.5 +18 V
IIK input clamping current VI< 0.5 V or VI >VDD + 0.5 V - 10 mA input voltage 0.5 VDD + 0.5 V
IOK output clamping current QSn outputs; VO< 0.5VorVO >VDD + 0.5 V - 10 mA
QPn outputs; VO <0.5V - 40 mA input leakage current - 10 mA output current QSn outputs - 10 mA
QPn outputs - 40 mA
Tstg storage temperature 65 +150 C
Tamb ambient temperature 40 +125 C
Ptot total power dissipation Tamb = 40 C to +125 C
DIP20 package [1]- 750 mW
SO20 package [2]- 500 mW
TSSOP20 package [3]- 500 mW power dissipation per output - 100 mW
NXP Semiconductors HEF4894B
12-stage shift-and-store register LED driver
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating conditionsVDD supply voltage 3 - 15 V input voltage 0 - VDD V
Tamb ambient temperature in free air 40 - +125 C
t/V input transition rise and fall rate VDD = 5V - - 3.75 s/V
VDD = 10 V - - 0.5 s/V
VDD = 15 V - - 0.08 s/V
Table 6. Static characteristicsVSS = 0 V; VI =VSS or VDD; unless otherwise specified.
VIH HIGH-level
input voltage IO < 1 A 5V 3.5 - 3.5 - 3.5 - 3.5 - VV 7.0 - 7.0 - 7.0 - 7.0 - VV 11.0 - 11.0 - 11.0 - 11.0 - V
VIL LOW-level
input voltage IO < 1 A 5V - 1.5 - 1.5 - 1.5 - 1.5 VV - 3.0 - 3.0 - 3.0 - 3.0 VV - 4.0 - 4.0 - 4.0 - 4.0 V
VOH HIGH-level
output voltage
QSn outputs; IO < 1 AV 4.95 - 4.95 - 4.95 - 4.95 - VV 9.95 - 9.95 - 9.95 - 9.95 - VV 14.95 - 14.95 - 14.95 - 14.95 - V
VOL LOW-level
output voltage
QSn outputs; IO < 1 AV - 0.05 - 0.05 - 0.05 - 0.05 VV - 0.05 - 0.05 - 0.05 - 0.05 VV - 0.05 - 0.05 - 0.05 - 0.05 V
QPn outputs; IO < 20 mAV - 0.75 - 0.75 - 1.5 - 1.5 VV - 0.75 - 0.75 - 1.5 - 1.5 VV - 0.75 - 0.75 - 1.5 - 1.5 V
IOH HIGH-level
output current
QSn outputs
VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 - 1.1 mA =4.6V 5V - 0.64 - 0.5 - 0.36 - 0.36 mA
VO = 9.5 V 10V - 1.6 - 1.3 - 0.9 - 0.9 mA
VO = 13.5 V 15V - 4.2 - 3.4 - 2.4 - 2.4 mA
IOL LOW-level
output current
QSn outputs
VO = 0.4V 5V 0.64 - 0.5 - 0.36 - 0.36 - mA
VO = 0.5V 10V 1.6 - 1.3 - 0.9 - 0.9 - mA
VO = 1.5V 15V 4.2 - 3.2 - 2.4 - 2.4 - mA input leakage
current
15 V - 0.1 - 0.1 - 1.0 - 1.0 A
NXP Semiconductors HEF4894B
12-stage shift-and-store register LED driver
10. Dynamic characteristicsIOZ OFF-state
output current
QPn output HIGH; =15V - 2 - 2 - 15 - 15 AV - 2- 2- 15 - 15 AV - 2- 2- 15 - 15 A
IDD supply current IO = 0A 5V - 5 - 5 - 150 - 150 AV - 10 - 10 - 300 - 300 AV - 20 - 20 - 600 - 600 A input
capacitance - - 7.5 - - - - pF
Table 6. Static characteristics …continuedVSS = 0 V; VI =VSS or VDD; unless otherwise specified.
Table 7. Dynamic characteristicsVSS = 0 V; Tamb = 25 C unless otherwise specified. For test circuit see Figure 10.
tPHL HIGH to LOW
propagation delay
CP to QS1;
see Figure6 [1] 132 ns + (0.55 ns/pF)CL -160 320 nsV 53 ns + (0.23 ns/pF)CL - 65 130 nsV 37 ns + (0.16 ns/pF)CL -45 90 ns
CP to QS2;
see Figure6V 92 ns + (0.55 ns/pF)CL -120 240 nsV 39 ns + (0.23 ns/pF)CL - 50 100 nsV 32 ns + (0.16 ns/pF)CL -40 80 ns
tPLH LOW to HIGH
propagation delay
CP to QS1;
see Figure6 [1] 102 ns + (0.55 ns/pF)CL -130 260 nsV 44 ns + (0.23 ns/pF)CL - 55 110 nsV 32 ns + (0.16 ns/pF)CL -40 80 ns
CP to QS2;
see Figure6V 102 ns + (0.55 ns/pF)CL -130 260 nsV 49 ns + (0.23 ns/pF)CL - 60 120 nsV 37 ns + (0.16 ns/pF)CL -45 90 ns
tPZL OFF-state to LOW
propagation delay
CP to QPn;
see Figure6 - 240 480 nsV - 80 160 nsV - 55 110 ns
STR to QPn;
see Figure7 - 140 280 nsV - 70 140 nsV - 55 110 ns
tPLZ LOW to OFF-state
propagation delay
CP to QPn;
see Figure 6 and 7 - 170 340 nsV - 75 150 nsV - 60 120 ns
STR to QPn;
see Figure7 - 100 200 nsV - 40 100 nsV - 35 70 ns
NXP Semiconductors HEF4894B
12-stage shift-and-store register LED driver[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
[2] ten is the same as tPZL and tdis is the same as tPLZ.
[3] tt is the same as tTLH and tTHL.
ten OE to QPn;
see Figure8 [2] -100 200 nsV - 55 110 nsV - 50 100 ns
tdis OE to QPn;
see Figure8 [2] - 80 160 nsV - 40 80 nsV - 30 60 ns transition time QS1, QS2;
see Figure6 [1][3] 35 ns + (1.00 ns/pF)CL - 85 170 nsV 19 ns + (0.42 ns/pF)CL -40 80 nsV 16 ns + (0.28 ns/pF)CL -30 60 ns pulse width CP; LOW and HIGH;
see Figure6 60 30 - nsV 30 15 - nsV 24 12 - ns
STR; HIGH;
see Figure7 80 40 - nsV 60 30 - nsV 24 12 - ns
tsu set-up time D to CP;
see Figure9 60 30 - nsV 20 10 - nsV 15 5 - ns hold time D to CP;
see Figure9 +5 15 - nsV 20 5 - nsV 20 5 - ns
fclk(max) maximum clock
frequency
CP; see Figure6 5V 5 10 - MHzV 11 22 - MHzV 14 28 - MHz
Table 7. Dynamic characteristics …continuedVSS = 0 V; Tamb = 25 C unless otherwise specified. For test circuit see Figure 10.
Table 8. Dynamic power dissipationPD can be calculated from the formulas shown. VSS = 0 V; tr = tf 20 ns; Tamb = 25 C. dynamic power
dissipation PD = 1200 fi + (fo CL) VDD2 Wfi = input frequency in MHz; = output frequency in MHz; = output load capacitance in pF;(fo CL) = sum of the outputs;
VDD= supply voltage in V.V PD = 5550 fi + (fo CL) VDD2 WV PD = 15000 fi + (fo CL) VDD2 W
NXP Semiconductors HEF4894B
12-stage shift-and-store register LED driver
11. Waveforms
Table 9. Measurement points V to 15V 0.5VDD 0.5VDD 0.1VO 0.9VO
