HEF4520BP-HEF4520BT Fast Delivery |IC PHOENIX CO.,LIMITED

HEF4520BP ,Dual binary counterFeatures and benefits Tolerant of slow clock rise and fall times Fully static operation 5 V, 10 ..
HEF4520BT ,Dual binary counterLogic diagram for one counterHEF4520B All information provided in this document is subject to legal ..
HEF4521BT ,24-stage frequency divider and oscillator
HEF4521BT ,24-stage frequency divider and oscillator
HEF4521BT ,24-stage frequency divider and oscillator
HEF4522BD ,Programmable 4-bit BCD down counter
HM6264AP-12 , 8192-word x 8-bit High Speed CMOS Static RAM
HM6264AP-12 , 8192-word x 8-bit High Speed CMOS Static RAM
HM6264AP-12 , 8192-word x 8-bit High Speed CMOS Static RAM
HM6264AP-12 , 8192-word x 8-bit High Speed CMOS Static RAM
HM6264AP-15 , 8192-word x 8-bit High Speed CMOS Static RAM
HM6264ASP-10 , 8192-word x 8-bit High Speed CMOS Static RAM

HEF4520BP-HEF4520BT
Dual binary counter
1. General description
The HEF4520B is a dual 4-bit internally synchronous binary counter. The counter has an
active HIGH clock input (nCP0) and an active LOW clock input (nCP1), buffered outputs
from all four bit positions (nQ0 to nQ3) and an active HIGH overriding asynchronous
master reset input (nMR).
The counter advances on either the LOW-to-HIGH transition of the nCP0 input if nCP1 is
HIGH or the HIGH-to-LOW transition of the nCP1 input if nCP0 is LOW. Either nCP0 or
nCP1 may be used as the clock input to the counter while the other clock input may be
used as a clock enable input. Schmitt trigger action makes the clock input highly tolerant
of slower clock rise and fall times. A HIGH on nMR resets the counter (nQ0 to
nQ3= LOW) independent of nCP0 and nCP1.
It operates over a recommended VDD power supply range of 3 V to 15 V referenced to VSS
(usually ground). Unused inputs must be connected to VDD, VSS, or another input.
2. Features and benefitsT olerant of slow clock rise and fall times Fully static operation 5 V, 10 V, and 15 V parametric ratings Standardized symmetrical output characteristics Specified from 40 C to +85 C Complies with JEDEC standard JESD 13-B
3. Ordering information
HEF4520B
Dual binary counter
Rev. 6 — 18 November 2011 Product data sheet
Table 1. Ordering information
All types operate from 40 C to +85 C.
HEF4520BP DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
HEF4520BT SO16 plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
NXP Semiconductors HEF4520B
Dual binary counter
4. Functional diagram
NXP Semiconductors HEF4520B
Dual binary counter
5. Pinning information
5.1 Pinning
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care;  = positive-going transition;  = negative-going transition.
Table 2. Pin description
1CP0, 2CP0 1, 9 clock input (LOW-to-HIGH triggered)
1CP1, 2CP1 2, 10 clock input (HIGH-to-LOW triggered)
1Q0 to 1Q3 3, 4, 5, 6 output
1MR, 2MR 7, 15 master reset input
VSS 8 ground supply voltage
2Q0 to 2Q3 11, 12, 13, 14 output
VDD 16 supply voltage
Table 3. Function table[1] H L counter advances  L counter advances X L no change  L no change L L no change  L no change X H nQ0 to nQ3 = LOW
NXP Semiconductors HEF4520B
Dual binary counter
7. Limiting values
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
8. Recommended operating conditions
Table 4. Limiting values
In accordance with the Absolute Maximum Rating System (IEC 60134).
VDD supply voltage 0.5 +18 V
IIK input clamping current VI< 0.5 V or VI >VDD + 0.5 V - 10 mA input voltage 0.5 VDD + 0.5 V
IOK output clamping current VO< 0.5 V or VO >VDD + 0.5 V - 10 mA
II/O input/output current - 10 mA
IDD supply current - 50 mA
Tstg storage temperature per output 65 +150 C
Tamb ambient temperature 40 +85 C
Ptot total power dissipation DIP16 package [1]- 750 mW
SO16 package [2]- 500 mW power dissipation - 100 mW
Table 5. Recommended operating conditions
VDD supply voltage 3 - 15 V input voltage 0 - VDD V
Tamb ambient temperature in free air 40 - +85 C
t/V input transition rise and fall rate VDD = 5V - - 3.75 s/V
VDD = 10 V - - 0.5 s/V
VDD = 15 V - - 0.08 s/V
NXP Semiconductors HEF4520B
Dual binary counter
9. Static characteristics
10. Dynamic characteristics
Table 6. Static characteristics
VSS = 0 V; VI = VSS or VDD unless otherwise specified.
VIH HIGH-level input voltage IO < 1 A 5 V 3.5 - 3.5 - 3.5 - V
10 V 7.0 - 7.0 - 7.0 - V
15 V 11.0 - 11.0 - 11.0 - V
VIL LOW-level input voltage IO < 1 A 5 V - 1.5 - 1.5 - 1.5 V
10 V - 3.0 - 3.0 - 3.0 V
15 V - 4.0 - 4.0 - 4.0 V
VOH HIGH-level output voltage IO < 1 A; =VSSor VDD
5 V 4.95 - 4.95 - 4.95 - V
10 V 9.95 - 9.95 - 9.95 - V
15 V 14.95 - 14.95 - 14.95 - V
VOL LOW-level output voltage IO < 1 A; =VSSor VDD
5 V - 0.05 - 0.05 - 0.05 V
10 V - 0.05 - 0.05 - 0.05 V
15 V - 0.05 - 0.05 - 0.05 V
IOH HIGH-level output current VO = 2.5 V 5 V - 1.7 - 1.4 - 1.1 mA
VO = 4.6 V 5 V - 0.52 - 0.44 - 0.36 mA
VO = 9.5 V 10 V - 1.3 - 1.1 - 0.9 mA
VO = 13.5 V 15 V - 3.6 - 3.0 - 2.4 mA
IOL LOW-level output current VO = 0.4 V 5 V 0.52 - 0.44 - 0.36 - mA
VO = 0.5 V 10 V 1.3 - 1.1 - 0.9 - mA
VO = 1.5 V 15 V 3.6 - 3.0 - 2.4 - mA input leakage current VDD = 15 V 15 V - 0.3 - 0.3 - 1.0 A
IDD supply current IO = 0A; =VSSor VDD
5 V - 20 - 20 - 150 A
10 V - 40 - 40 - 300 A
15 V - 80 - 80 - 600 A input capacitance - - - - 7.5 - - pF
Table 7. Dynamic characteristics
VSS = 0 V; Tamb = 25 C; for test circuit see Figure 6; unless otherwise specified.
tPHL HIGH to LOW
propagation delay
nCP0, nCP1  nQn;
see Figure5
5 V [1] 83 ns + (0.55 ns/pF)CL - 110 220 ns
10 V 39 ns + (0.23 ns/pF)CL - 50 100 ns
15 V 32 ns + (0.16 ns/pF)CL -40 80 ns
nMR  nQn;
see Figure5
5 V 48 ns + (0.55 ns/pF)CL - 75 150 ns
10 V 24 ns + (0.23 ns/pF)CL -35 70 ns
15 V 17 ns + (0.16 ns/pF)CL -25 50 ns
NXP Semiconductors HEF4520B
Dual binary counter
[1] The typical values of the propagation delay and transition times are calculated from the extrapolation formulas shown (CL in pF).
tPLH LOW to HIGH
propagation delay
nCP0, nCP1  nQn;
see Figure5
5 V [1] 83 ns + (0.55 ns/pF)CL - 110 220 ns
10 V 39 ns + (0.23 ns/pF)CL - 50 100 ns
15 V 32 ns + (0.16 ns/pF)CL -40 80 ns transition time nQn; see Figure5 5 V [1] 10 ns + (1.00 ns/pF)CL - 60 120 ns
10 V 9 ns + (0.42 ns/pF)CL -30 60 ns
15 V 6 ns + (0.28 ns/pF)CL -20 40 ns pulse width nCP0 input LOW;
minimum width;
see Figure5
5 V 6030- ns
10 V 30 15 - ns
15 V 20 10 - ns
nCP1 input HIGH;
minimum width;
see Figure5
5 V 6030- ns
10 V 30 15 - ns
15 V 20 10 - ns
nMR input HIGH;
minimum width;
see Figure5
5 V 3015- ns
10 V 20 10 - ns
15 V 16 8 - ns
tsu set-up time nCP0  nCP1;
see Figure5
5 V 5025- ns
10 V 30 15 - ns
15 V 20 10 - ns
nCP1  nCP0;
see Figure5
5 V 5025- ns
10 V 30 15 - ns
15 V 20 10 - ns
trec recovery time see Figure5 5 V 5025- ns
10 V 30 15 - ns
15 V 20 10 - ns
fmax maximum
frequency
nCP0, nCP1;
see Figure5
5 V 8 16 - MHz
10 V 1530- MHz
15 V 2040- MHz
Table 7. Dynamic characteristics …continued
VSS = 0 V; Tamb = 25 C; for test circuit see Figure 6; unless otherwise specified.
Table 8. Dynamic power dissipation PD
PD can be calculated from the formulas shown. VSS = 0 V; tr = tf  20 ns; Tamb = 25 C. dynamic power
dissipation
5 V PD = 850  fi + (fo  CL)  VDD2 fi = input frequency in MHz,
fo = output frequency in MHz,
CL = output load capacitance in pF,
VDD = supply voltage in V,
(fo  CL) = sum of the outputs.
10 V PD = 3800  fi + (fo  CL)  VDD2
15 V PD = 10200  fi + (fo  CL)  VDD2
NXP Semiconductors HEF4520B
Dual binary counter
11. Waveforms

Partno	Mfg	Dc	Qty	Available	Descript
HEF4520BP	NXP	N/a	1000	avai	Dual binary counter
HEF4520BT	PH	N/a	950	avai	Dual binary counter